FIR Filter On FPGA

Hi all

I want to design a 1024 poles FIR filter on FPGA. But I had n experiences on large scale FPGA programming. Can anybody tell me whic chip should I use?


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Both Altera and Xilinx sell FPGAs which are in some sense designed for DSP applications. How large an FPGA you need depends on other parameters which you have not specified, such as how many bits per sample, and how many clocks are available per sample. Altera and Xilinx offer development tools which have a variety of automated tools to help you do FPGA-based DSP, of course, none are as good as hand-coding. For many applications, though, they are enough.

Regarding cost, generally the older chips (2 or more generations old) will cost more per CLB than new chips. Then again, there are more development boards and tools available to support the older chips.

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Jim George

You need more information before you can decide on an approach:

what is the sample rate? what is the clock rate? can you use a multiplied clock? How many bits per sample? How many bits do you need per tap coefficient?

The number of taps is high enough that a fast convolution using overlap and add FFTs might yield better density.

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Ray Andraka

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