FPGA clock gating ? Or how to avoid it in this case ?

Hi,

So, my problem :

I have a netlist of a module. I can't change it, it comes from a big manufacturer and they have no interest whatsoever in really helping us especially since we're not really paying customer but more "academic researcher" ...

This takes a stream of continous data, and they have to be continuous,

1 each clock (there are pauses but very far apart) and they don't have "enable" on their registers. Now, the rest of my chain only can process 2 data in 3 cycles ...

So an idea would be to "block" the rising edge 1 cycle every 3 cycle, maybe using a bufgmux ? Also, I'm considering using the "divide clock by 1.5" circuit by Peter Alfe, and use some sort of clock domain crossing technique to cross my 2 data back and forth. Any suggestion on this ?

FYI: I'm working in a virtex4 FPGA.

Thanks for any insight ...

Sylvain