FPGA Clock signal

i would like to ask how can i capture the FPGA master clock signal in the oscilloscope? Bcos in the data sheet, it indicates that the master clock is located at pin N9 which is not accessible externally. please help. thanks a million

Reply to
raullim7
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Hi,

Either you have to measure at the clock oscillator or route the clock input out on a pin that is externally accessible. If you route through you will get internal IO buffer delays added to your clock signal.

/Roger

Reply to
roger

Are you *sure* this signal is not externally accessible? Typically the BGA package has a matrix of pads and vias. The via for the clock signal should be exposed on the back of the board, ready for a steady hand to probe the clock right there "at" the package ball.

Reply to
John_H

i am using the XEM3010 board. really have no idea how to tap the signal. please help..

Reply to
raullim7

Is there a schematic available in the XEM3010 documentation? If so, it should be possible to find another pin somewhere else on the board where the same clock signal can be probed with your oscilloscope.

John LeVieux

Reply to
John LeVieux

I use BRK3010 the BreakOut Board for XEM3010 and it maps most pins to an easy to probe test points. N9 is not mapped but I remember measuring the PLL CLKA output on the XCLK1 Test point of the BRK3010 board.

Reply to
Naive_Algorithm

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