Hi, The static timing analysis report for my design is as follows:
From: DAT_FSM/FULL_TEMP:CLK To: DAT_FSM/count[10]:D data required time 14.609 data arrival time 15.146 slack -0.537
Could any one please suggest me the techniques to avaoid negative slack. Please let me know the relavent material available.
Thanks in advance.
Regards, HimaSSK.
Try praising Bob.
No seriously... all that negative slack means is that you have too much logic between flip-flop stages. So, you should simplify and/or pipeline your circuit. (In fact, it could be a problem with I/O, but in this case it looks like it's probably an internal path.)
Your timing analysis tool should be giving you a list of the nets on the "critical paths" in your design. Look at the logic you've designed and think carefully about whether it is overcomplicated, whether you can split a computation or control decision into two stages to be performed in separate clock cycles. Without specific details of what the circuit does, it's quite hard to make more specific suggestions.
It might help to specify what tools you are using and what device you are targeting. I'm just a little bit concerned that the "From:" net specifies a clock... but this may be just the way your tool is reporting the timing violation.
Good luck,
-Ben-
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