Does xiling cpld's need a power supply bypass cap?

Every chip, everywhere should have bypass caps on all power pins.

Period.

If the manufacturer says not to do it, then you should comply, but reluctantly (re: Microchip Vpp line, which is driven by the programmer and Must Have Fast Edges).

If it has more than one power pin, it should have more than one cap. The rule of thumb is to have one cap per power pin. Extras never hurt. If the chip designers were paying attention you'll find power and ground pins in pairs; you should lay out your board so you have short runs to the caps. If the chip designers were _really_ paying attention you'll find a section of the data sheet that specifies how the bypass caps should be laid out. Follow it.

If you don't, I doubt you will even be able to program it. The charge pump for the flash programming will fail.

Always consult the datasheet. You may need more than 0.1uF bypass caps. I will usually use a range from 0.01uF to 10uF and for more powerful FPGAS up too 1000uF. This is something that can be determined using the XPower tools from Xilinx ISE. For prototype you may not need to go crazy on bypassing, but at a min 1 0.1uF per Power Pin as close to to the power pin with a good low impeadance via (or three) to the ground plane.

Also, the amount of bypassing needed will depend on the power supply used, the routing of the power to the chip and how close it is to you IC. If you use a switching PS you will need good high quality bypass caps to clean out the high frequency switching noise. If the power supply has a slow response to current spikes you will need more larger caps to fill in where the Power supply cannot.

Keeping the PS as close to the load will always improve power quality and also using large tracks or better yet power planes in pairs. Even if it is a pour on the top and bottom.

Granted Xilinx CPLDs are great for low power consumption, but during flashing, they can draw a significant load on the supplies.

--Brian

able to program it. The charge

messagenews:urGdnQTweMpjDCrYnZ2dnUVZ snipped-for-privacy@web-ster.com...

The spin I heard, for the reason for corner pins, was to allow better Power Supply grid layouts. Yes, even using AC mains terminology & thinking :)

In those days, multi-layer PCBs were rare, and WIDE traces were also needed, to handle the Amps needed on a card with many TTL devices. So, no trace-between-pins fancy stuff on the Supply traces. Some cards used physical BUS Rails, to run the power/gnd supplies.

-jg

The "good reason" is it made it possible to use REAL bus bars to distribute power and ground on wire-wrap boards, and wide power/ground tracks between rows of chips on 2-sided boards. For 7400-series logic, the penalty was really small, with 10 ns Tr - Tf. As the move to faster and faster CMOS happened, it got to be a problem.

Jon