I'm working on a design that needs to be able to write to a DDR ram at
133MHz but only needs to read back the data at a slower rate. I thought I could greatly ease the design by slowing down the clock on reads to say 66MHz. This really opens up my read timing budget. Doing fast writes is easier because I can use a 90 degree shifted clock to drive the DQS lines.The problem is I'm not sure how to create a constraints file that enforces the timing required for different read and write clock speeds. Anybody have any ideas? I'm using a Spartan-3[E] and ISE 8.1.
Thanks, David Carr