Typical bus interface consists of CS, ADDR, DATA, RD and WR signals. The bus transfer type designator may be whether read or write, not both simulataneously. That is, RD and WR are mutually exclusive. Why do most bus interfaces separate read and write signals?
Bus interface - read, write signals
Mar 07, 2004
2 Replies
It's probably left over from directly interfacing to ROMs or SRAMs or Flash chips. It's easy to build small/simple logic if you use the trailing edge of RD or WR as the clock. Think of something like a printer port and look in your old (ancient) data books for TTL/LS era parts.
If you only have one of RD and WR, then you also need a clock.
You might try to use CS as the clock, but the access time on ROM/RAMs from CS is usually (much) longer than the access time from RD. (CS typically shifts the whole chip into low power mode. It takes a while to wake up again.)
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
you missed bus idle...
bus
bus
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required