cutting down opb_clk cycles while read-write BRAM-DDR in FPGA

Hello all,

I am working on a project which involves a simple BRAM, OPB-PLB, Microblaze/PPC, and opb_ddr_sdram controller. I am reading 1280 bytes of data from bram (32 bits each read, thus a total of 320 reads) and writing it to DDR sdram. i am using Xilinx standalone OS. i use the command XIo_in32(addr) to read from bram and use XIo_out32(addr,data) to write to DDR sdram controller.

here is the c code i use to write to ddr.

for(p=0;p

Reply to
chakra
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Step b: Why recalculate the destination address? Just increment to avoid the multiply.

for(p=3D0;p

Reply to
Ed Prochak

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