FSL read/write problems

Hi all,

I'm trying to implement a correlator as a coprocessor on the FSL bus. The first thing I've done is generate the FSL example using the create peripheral wizard in EDK 8.1 and hooked it up to the MicroBlaze. When I do a blocking write or read the MB stalls - my understanding is that this will happen if the FSL FIFO is full or empty respectively, but it happens the first time I write to it, so the FIFO should not be full.

If I use non-blocking reads and writes and check the error and invalid flags after each one using fsl_isinvalid() and fsl_iserror() - see code below - everything seems normal but the output is always zero. Am I implementing the error checking macros correctly?

#define write_into_fsl(val, id) nputfsl(val, id) #define read_from_fsl(val, id) ngetfsl(val, id)

#define WRITE_FSL_TEST_0(val) write_into_fsl(val, XPAR_FSL_FSL_TEST_0_INPUT_SLOT_ID) #define READ_FSL_TEST_0(val) read_from_fsl(val, XPAR_FSL_FSL_TEST_0_OUTPUT_SLOT_ID)

void fsl_test_app( unsigned int* input_0, /* Array size = 2 */ unsigned int* output_0 /* Array size = 2 */ ) { int i; Xuint8 is_error = 0; Xuint8 is_valid = 0;

print("Entering fsl_test_app \r\n");

//Start writing into the FSL bus for (i=0; i

Reply to
David
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Hi,

Can you show the .mhs where you have connected your FSL core with Microblaze?

Göran Bilski

Reply to
Göran Bilski

Hi G=F6ran,

Thanks for your reply, here are the relevant parts of the .mhs file:

BEGIN microblaze PARAMETER INSTANCE =3D microblaze_0 PARAMETER HW_VER =3D 4.00.a PARAMETER C_USE_FPU =3D 0 PARAMETER C_DEBUG_ENABLED =3D 1 PARAMETER C_NUMBER_OF_PC_BRK =3D 2 PARAMETER C_FSL_LINKS =3D 1 BUS_INTERFACE DLMB =3D dlmb BUS_INTERFACE ILMB =3D ilmb BUS_INTERFACE DOPB =3D mb_opb BUS_INTERFACE IOPB =3D mb_opb BUS_INTERFACE SFSL0 =3D fsl_v20_0 BUS_INTERFACE MFSL0 =3D fsl_v20_1 PORT CLK =3D sys_clk_s PORT DBG_CAPTURE =3D DBG_CAPTURE_s PORT DBG_CLK =3D DBG_CLK_s PORT DBG_REG_EN =3D DBG_REG_EN_s PORT DBG_TDI =3D DBG_TDI_s PORT DBG_TDO =3D DBG_TDO_s PORT DBG_UPDATE =3D DBG_UPDATE_s END

BEGIN fsl_v20 PARAMETER INSTANCE =3D fsl_v20_0 PARAMETER HW_VER =3D 2.00.a PARAMETER C_EXT_RESET_HIGH =3D 0 PARAMETER C_IMPL_STYLE =3D 1 END

BEGIN fsl_v20 PARAMETER INSTANCE =3D fsl_v20_1 PARAMETER HW_VER =3D 2.00.a PARAMETER C_EXT_RESET_HIGH =3D 0 PARAMETER C_IMPL_STYLE =3D 1 END

BEGIN fsl_test PARAMETER INSTANCE =3D fsl_test_0 PARAMETER HW_VER =3D 1.00.c BUS_INTERFACE MFSL =3D fsl_v20_0 BUS_INTERFACE SFSL =3D fsl_v20_1 PORT reset_out =3D fsl_test_0_reset_out PORT state_debug =3D fsl_test_0_state_debug END

Cheers,

David

Reply to
David

Hi David,

Please specify the connections for clock and reset ports of FSL

-Felix

Hi Göran,

Thanks for your reply, here are the relevant parts of the .mhs file:

BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.a PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 2 PARAMETER C_FSL_LINKS = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb BUS_INTERFACE SFSL0 = fsl_v20_0 BUS_INTERFACE MFSL0 = fsl_v20_1 PORT CLK = sys_clk_s PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s END

BEGIN fsl_v20 PARAMETER INSTANCE = fsl_v20_0 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PARAMETER C_IMPL_STYLE = 1 END

BEGIN fsl_v20 PARAMETER INSTANCE = fsl_v20_1 PARAMETER HW_VER = 2.00.a PARAMETER C_EXT_RESET_HIGH = 0 PARAMETER C_IMPL_STYLE = 1 END

BEGIN fsl_test PARAMETER INSTANCE = fsl_test_0 PARAMETER HW_VER = 1.00.c BUS_INTERFACE MFSL = fsl_v20_0 BUS_INTERFACE SFSL = fsl_v20_1 PORT reset_out = fsl_test_0_reset_out PORT state_debug = fsl_test_0_state_debug END

Cheers,

David

Reply to
Felix Pang

Hi,

You need to connect the system clock to the fsl_v20 modules. They are non clocked right now.

One good trick is always to look at the top level vhdl file in the hdl directory. It's called system.vhd

In that file you will see what signals are connected to what and it this case you should be able to see that the fsl bus doesn't have any clock connected.

Göran Bilski

Reply to
Göran Bilski

Thanks for your help guys, that fixed it. Interesting that the EDK system assembly GUI doesn't hook up clock and reset by default...

Cheers,

David

G=F6ran Bilski wrote:

Reply to
David

Hi David,

It is decided by the MPD file of the IP. Refer to the MPD of FSL you should see that the default connections of clock and reset are left blank.

-Feilx

Cheers,

David

Göran Bilski wrote:

Reply to
Felix Pang

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