simulation works fine but the actual chip doesnt work

I'm not sure how anyone can help you with such a terse description of what you're trying to do and, worse still, what results you are getting?!?

For example, if would be helpful to explain - at the very least - what you're actually measuring, what the measurements are, and how they differ to what you expect.

What have you tried - common-sense troubleshooting should provide

First step is to narrow down where the problem lies. Can you implement a register and successfully read/write over PCI? Can you provide a fixed pattern to the data-out register on the UART and see that? Can you seed the FIFO with fixed data and see that? And so on...

As for simulation vs synthesis, most commonly it's due to the simulation's stimulus (inputs) being different to (or only a small, non-representative sample of) the real-world signals. eg. in your case PCI bus transactions, or clocking, such as the phase relationship between your clock domains. Another possibility is that you're relying on non-synthesisable elements of your HDL for 'correct' operation under simulation.

Regards,

Hello Mark,

I have done many runs on the actual chip and also the smulation. Here are the major differences that I have noticed and are a possible cause of failure for the actual chip.

In the simulation, the transmission line of the UART is at HIGH when NOT transmitting anything, when I provide it with some data value and a write signal, It transmits it and then goes back high again. When the transmission is completed another signal called UART_RDY is asserted and that indicates that I can load in the next data value.

In the actual synthesised design, the TX line keeps transmitting some random pattern over and over again, and is not held at HIGH state when I power the chip on. In other words the UART_RDY signal is never asserted, which implies that I cannot load data values from the PCI bus, as it is always waiting for the UART_RDY signal to be asserted.

I have very little experience with ASIC/FPGA design, hence I am not able to come up with a way to hold the TX line at HIGH when the chip powers up. I have to stop the TX line from behaving in a random manner so that I can read the UART_RDY signal and then load data values from the PCI bus into it.

Please advise.

Thank you,

Sandeep

I can't imagine the TX line state has anything to do with the UART_RDY signal - there shouldn't be any feedback required here. UART_RDY I would've thought depends only on the state machine of the transmitter, and when the last bit is clocked out of the transmit register, then UART_RDY is asserted.

The fact that TX line isn't held high is a problem - and given the behaviour I'd suspect clocking problems? Have you checked the clock to the UART with the logic analyzer functionality of your synthesis tools?

BTW what's the UART core doing when there's nothing to xmit? Is it holding TX high itself, or tri-stating and assuming you have a pullup?

Is this your UART design BTW?

Regards,

Hello Mark,

Yes you are right, the UART_RDY depends on the state of the transmission. What I meant to say was that when the transmission of the data ends, TX goes high and UART_RDY is asserted. This is a design I found on the web. It is originally from Quicklogic, but I modified it so that it transmits 8 bit data and then another 8 bit data before the state machine asserts the UART_RDY. Below is the part of the code:

BEGIN

--// Paritycycle = 1 on next to last cycle, this means when tsr[1] gets tag2.

paritycycle

Hi Mark,

here is the link for the UART.

Thank you,

Sandeep

Hi Mark,

Any advise ?

Thanks,

Sandeep