Can't assign pins in Webpack 8.2i schematic design

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After further attempts to use Xilinx Webpack 8.2i for Coolrunner XPLA3 I
have discovered the following situation which makes it rather disappointing:

1.  I have a very simple schematic design which uses logic library
elements such as "FDC" and basic logic gates.

2.  The resulting Verilog file created from the schematic encapsulates
the FDC in a Verilog module wrapper at the top of the file, with my
design as a module following.  (I have pasted an example text below of
the .v(f) file)

3.  Because the FDC wrapper module appears first in the file, it appears
that the PACE tool thinks that it should assign package pins to the IOs
for the FDC rather than my design's IOs.  Ie, PACE gives me the list of
FDC IOs:  C, CLR, D, Q to which to assign package pins.  This is clearly
not what is desired.

4.  The Xilinx Constraints Editor no longer allows pin assignments,
because it interprets all location constraints as read-only.

It seems that if I create a .ucf file to assign pins by hand with the
"Edit Constraints (text)" then the resulting file will work to cause the
desired pin assignments when implementing the design.

But this is pretty strange.  The inability of the Xilinx Constraints
Editor to assign location constraints to ports, and the inability to use
PACE make 8.2i an effective downgrade from the 5.2i I was using previously.

Is anyone else attempting to do schematic design with Webpack 8.2i and
seeing the same behavior?

Thanks for input.


// Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 8.2i
//  \   \         Application : sch2verilog
//  /   /         Filename : pd3state.vf
// /___/   /\     Timestamp : 01/25/2007 15:28:18
// \   \  /  \
//  \___\/\___\
//Command: D:\Xilinx\bin\nt\sch2verilog.exe -intstyle ise -family xpla3
-w E:/xilinx/fast-shutter/WebPack8.2i/012507/pd3state.sch pd3state.vf
//Design Name: pd3state
//Device: xpla3
//    This verilog netlist is translated from an ECS schematic.It can be
//    synthesized and simulated, but it should not be modified.
`timescale 1ns / 1ps

module FDC_MXILINX_pd3state(C,

     input C;
     input CLR;
     input D;
    output Q;

    wire XLXN_5;

    GND I_36_55 (.G(XLXN_5));
    FDCP U0 (.C(C),
`timescale 1ns / 1ps

module pd3state(M1_REF_IN,

     input M1_REF_IN;
     input M1_SYNC_BUF;
    output M1_SYNC;
    output PFD1_QHI;
    output PFD1_QLO;

    wire XLXN_3;
    wire XLXN_4;
    wire XLXN_5;

    FDC_MXILINX_pd3state XLXI_1 (.C(M1_SYNC),
    // synthesis attribute HU_SET of XLXI_1 is "XLXI_1_0"
    FDC_MXILINX_pd3state XLXI_2 (.C(M1_REF_IN),
    // synthesis attribute HU_SET of XLXI_2 is "XLXI_2_1"
    AND2 XLXI_3 (.I0(PFD1_QLO),
    VCC XLXI_5 (.P(XLXN_4));
    VCC XLXI_6 (.P(XLXN_5));


Good day!

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Re: Can't assign pins in Webpack 8.2i schematic design
I am having this exact same problem, but using schematic entry and automatic
VHDL from that. I have spent hours trying to get PACE to look at MY ports. It
works if I create a new project with just a schematic containing an inverter and
one in and one out pin. PACE lets me assign the two clock pins. But when I add
even one part such as a counter, then PACE says that it can not apply my
constraints and my pins and their nets no longer show up in PACE's list of nets.
Instead the various unused pins of library parts that I have used, are what show
up as nets in PACE.

One hint perhaps, is that I get warnings about the source of the ports and
entities definitions, being changed from the schematic to the generated vhdl
file. I think that this is an encapsulation issue.

All this, yet the design actually works in hardware. It's an inverter for a
crystal clock, that then drives three 8-bit counters to divide down for a
blinking LED.

Anyone know how to fix this ?

- Bruce

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