Assign FPGA pins to submodule

I'm currently working with ISE 7.1

I'd like to be able to assign FPGA pins to a submodule either via a ucf file, or (preferably) via assigning properties to nets within the module.

To expand-- I'm creating some modules for use as library blocks in a classroom setting. These blocks will always be mapped to static FPGA pins, corresponding to LEDs, pushbuttons, etc, so I'd like to be able to just drag and drop them onto a schematic, without having to create top level I/O markers.

I know this was possible in ISE 2.1 (the version the class is currently using), but is it still possible in 7.1?

Thanks, Matt

Reply to
Matt Fornero
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Before you go too far with this, you may want to use the schematics in

7.1i a bit. You may not want to use the new schematics at all...

Just my 2c

Gabor

Reply to
Gabor

intuitive as 2.1

However, our goal is to keep the lab assignments relatively static while migrating to the new platform, so the schematic tool will need to used for the relative future.

I wouldn't have a problem writing the I/O submodules in verilog, if that would allow me to assign pins-- my problem seems to be that the implementation tool ignores any constraints (either via net properties in the schematic or a .ucf file associated with the submodule) set on submodules entirely.

Is there some setting that causes the tool to evaluate constraints for submodules that I'm not setting?

Reply to
Matt Fornero

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