I was aware that there is a flag which can disenable Design Compiler to write Assign statement. My NCVerilog gave me warning on Assign statement when performing gate level simulations.
Many thanks in advance.
I was aware that there is a flag which can disenable Design Compiler to write Assign statement. My NCVerilog gave me warning on Assign statement when performing gate level simulations.
Many thanks in advance.
Frank, See:
HTH Ajeetha
I love this quote: "It's always been my dream to give my customers a choice between ViewLogic & ViewLogic." That's a nice perch to sit on!
Jerry
-- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
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