Dear Sir or Madam,
I have a question concerning Modelsim:
In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd" as U1
In the attached macro I add waves. These waves are inputs and outputs of the module "packetfile_ctrl.vhd". But what if I want to view internal signals? For example the internal signal last_block: If I write the following command in my macro I do not get a wave of this signal "add wave sim:/tb_packetfile_ctrl/u1/last_block" So how can I add an internal signal? Is there an alternative way without using the macro (this means adding a wave belatedly when the waveform - editor is already opened) ?
Thank you for your help.
Best regards Andrés Vázquez G&D
MACRO: cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim vlib modelsim_work vmap work modelsim_work vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL vcom -93 -reportprogress 300 -work work {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho} vcom -93 -reportprogress 300 -work work {H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd} view signals view wave vsim work.TB_PACKETFILE_CTRL add wave sim:/tb_packetfile_ctrl/u1/P_clk_in add wave sim:/tb_packetfile_ctrl/u1/P_clk_out add wave sim:/tb_packetfile_ctrl/u1/Reset add wave sim:/tb_packetfile_ctrl/u1/Write add wave sim:/tb_packetfile_ctrl/u1/Read add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????