Hello, I'm trying to simulate my design in modelsim and i'm trying to find out if it is possible to choose the set_up delays of the clock signals in a simulation.
Indeed in my simulation the clock edge are too fast (0 ns) so it creates errors in my simulation which will not appears in a real design due to set_up delays.
I'm trying to use ' vsim -sdf' function but it don't seems to works.
Thancks in advance for answering.
Clock signals do not have 'setup delays'
The 'clock edges' will always be 0ns in simulation.
Setup times (and hold times) are requirements that must be met in order for the design to work. If you violate the setup or hold time requirements then your design will not be guaranteed to work. From your description, it sounds like the inputs to your design are not meeting the timing requirements relative to your clock.
Look at your testbench code that generates the inputs to your design. Are the inputs stable relative to the clock for the entire setup time prior to the clock all the way through to the hold time after the clock? I'm guessing that they're not, the solution is not some 'clock setup delays', the solution is one of the following:
- Properly model the other inputs so that they transition at the proper time relative to the clock that will happen in the system (Hint: If those signals are clocked by that same clock signal they will not be transitioning exactly at the rising edge of the clock....they will happen some Tco time later).
- If the inputs in your system have no timing relationship relative to the clock then they are asynchronous to the clock in which case your design needs to take that properly into account by synchronizing them. By definition, those synchronizing flip flops will occasionally have their input setup/hold times violated which is OK (which is why the word 'properly' is in the previous sentence in '...properly into account...'.
In any case you don't need set_up delays on clock signals....whatever that really is supposed to mean
KJ
That's exactly my problem. In my simulation the edge clock and my signal arrives exactly at the same time. In fact I the signal is an Write of an fifo, and I use a state machine to create a '1' during a period. But When this signal goes '1' to '0' it maps exacly whith the rising'edge of my clock, and I'm writing two data in my FIFO when 1 want just one. And I thinck in a real design i won't append, due to delay in the flip-flop. (Sorry about my English I try to do my best)
So if i have understand what you said it not feasible to change 'in modelsim' that, so I need to include delay time in my test-bench?
Thancks for your answer
I am guessing that you are doing a pre-implementation simulation of your code. These simulation don't have any idea about timing. If you want to add this information so it makes it easier for you to undestand the results, add delays in the desired assignments in your code. In the case of Verilog to add a 3 time unit delay:
always @(posedge clk) begin if(en) data_FF signal arrives exactly at the same time. In fact I the signal is an
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