Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Compiling Xilinx libraries for ModelSim PE 10.4 simulation out of ISE 8.2i
Simulation of your project written in ISE 8.2i, for those using old tools f or whatever reason, must first compile the necessary libraries. One may str uggle with getting simulation of their project...
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9 years ago
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[JOB POSTING] Sought: Freelance FPGA PCB Designer
We are searching for a freelance PCB designer that is familiar with FPGA, D DR3, LVDS, SMPS, Analog-to-Digital converters, USB, PCIe, Gigabit Transceiv ers, etc, board layout and schematic design. Has...
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9 years ago
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DDS
What is the best way to implement a multi channel DDS. I need a DDS that has 8 channels that are time-multiplexed. I am using a Sparatn 6. Thanks --------------------------------------- Posted through
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9 years ago
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IIC in microblaze
hello I need your help please. I want to connect a gyrocompas(HMC5883L) with a microblaze which is done by I2c and as microblaze does not have the bus I2c. I must add it as a peripheral to the...
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9 years ago
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Program Xilinx with Altera JTAG Programmer?
Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less...
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9 years ago
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Microblaze problem with FSL core
Hi guys, I'm not sure this is the right place to ask this question, but I found no answers to it on xilinx forums. Hope you can help me! intro: I work with atlys board. using Microblaze processor....
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9 years ago
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An Altera CPLD "JTAG Unlocker"
Hi There, From time to time I see people having Altera CPLDs on the "JTAG Lockout" st atus. I have a few EPM7128s on this state myself. I wonder how difficult would it be to create an...
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9 years ago
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New invention: Systematic method of coding wave pipelined circuits in HDL
Hi Jim, glen, JK, rickman, Mike, Andy, I have filed a provisional patent application: "Systematic method of coding wave pipelined circuits in HDL". If it is proved correct, the patent will introduce 1...
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9 years ago
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FPGA Project -
Looking for someone to work on a project. Quick Notes 1. PCI FGPA Card (standard off the shelf is possible) 2. Interface to decryption engine 3. Multiple decryption engines, as many as the FPGA will...
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9 years ago
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Inferring F7 / F8 Mux in Xilinx
I'm posting this here for my own future reference. If you infer a mux with fewer than 2**n inputs, Vivado won't infer the F7 or F8 muxes. Here is the trick to make sure you get the best synthesis....
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9 years ago
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Kintex UltraScale board with two DDR4 interfaces?
Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 controllers (i.e., a board where there is more than one address bus for the DDR4...
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9 years ago
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Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea
The Embedded System on Chip Lab of the Hallym University seeks to recruit p romising PhD and MSc research students. The selected students will conduct research in the [GPU based Parallel Computing]...
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9 years ago
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Re: Open Source GPGPU core
I tried building your toolchain on both a 32 and 64 bit amd Ubuntu 14.10 system and get: Linking CXX shared library ../../../lib/ Python script sym-linking LLDB Python API Program error: Invalid...
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9 years ago
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Re: Dynamic partial reconfiguration on Spartan 3 chips
yes i am in need of DPR on spartan 3,Can you help?
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9 years ago
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processor core validation
Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code (vhdl) and a simulation environment to load programs and execute...
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9 years ago
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