Microchip PIC18 datasheet: 28.4.3 Timing diagrams and specifications

28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 28-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 28-8: EXTERNAL CLOCK TIMING REQUIREMENTS

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

2: When VDD >= 3.3V, the maximum crystal or resonator frequency is 25 MHz (or 24 MHz with PLL prescaler). When 2.0V < VDD < 3.3V, the maximum crystal frequency = (16.36 MHz/V)(VDD – 2.0V) + 4 MHz.

TABLE 28-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 5.5V)

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

TABLE 28-10: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)

Legend: Shading of rows is to assist in readability of the table.
Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
2: INTRC frequency after calibration.
3: Change of INTRC frequency as VDD changes.

FIGURE 28-6: CLKO AND I/O TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS

† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

FIGURE 28-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING

Note: Refer to Figure 28-4 for load conditions.

FIGURE 28-8: BROWN-OUT RESET TIMING

TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS

FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Note 1: Requires the use of Parameter 73A. Note 2: Only if Parameter 71A and 72A are used.

FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Note 1: Requires the use of Parameter 73A. Note 2: Only if Parameter 71A and 72A are used.

FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Note 1: Requires the use of Parameter 73A. Note 2: Only if Parameter 71A and 72A are used.

FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Note 1: Requires the use of Parameter 73A. Note 2: Only if Parameter 71A and 72A are used.

FIGURE 28-15: I²C™ BUS START/STOP BITS TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-19: I²C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

FIGURE 28-16: I²C™ BUS DATA TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-20: I²C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I²C™ bus device can be used in a Standard mode I²C bus system but the requirement, TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCL line is released.

FIGURE 28-17: MASTER SSP I²C™ BUS START/STOP BITS TIMING WAVEFORMS

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-21: MASTER SSP I²C™ BUS START/STOP BITS REQUIREMENTS

Note 1: Maximum pin capacitance = 10 pF for all I²C™ pins.

FIGURE 28-18: MASTER SSP I²C™ BUS DATA TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-22: MASTER SSP I²C™ BUS DATA REQUIREMENTS

Note 1: Maximum pin capacitance = 10 pF for all I²C™ pins.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system but parameter #107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released.

FIGURE 28-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 28-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

FIGURE 28-21: USB SIGNAL TIMING

TABLE 28-25: USB LOW-SPEED TIMING REQUIREMENTS

TABLE 28-26: USB FULL-SPEED REQUIREMENTS

FIGURE 28-22: STREAMING PARALLEL PORT TIMING (PIC18F4455/4550)

Note: Refer to Figure 28-4 for load conditions.

TABLE 28-27: STREAMING PARALLEL PORT REQUIREMENTS (PIC18F4455/4550)

TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL) PIC18LF2455/2550/4455/4550 (INDUSTRIAL)

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

FIGURE 28-23: A/D CONVERSION TIMING

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 28-29: A/D CONVERSION REQUIREMENTS

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.

NOTES: