Microchip PIC18 datasheet: MOVFF Move f to f

MOVFF Move f to f

Syntax:
MOVFF fs,fd

Operands:
0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095

Operation:
(fs) → fd

Status Affected:
None

Encoding:
1st word (source)
2nd word (destin.)
1100 ffff ffff ffffs 1111 ffff ffff ffffd

Description:
The contents of source register ‘fs’ are moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh.
Either source or destination can be W (a useful special situation).
MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port).
The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.

Words:
2

Cycles:
2

Q Cycle Activity:

Example:
MOVFF REG1, REG2

Before Instruction
REG1 = 33h
REG2 = 11h

After Instruction
REG1 = 33h
REG2 = 33h

MOVLB Move Literal to Low Nibble in BSR

Syntax:
MOVLW k

Operands:
0 ≤ k ≤ 255

Operation:
k → BSR

Status Affected:
None

Encoding:
0000 0001 kkkk kkkk

Description:
The eight-bit literal ‘k’ is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains ‘0’ regardless of the value of k7:k4.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
MOVLB 5

Before Instruction
BSR Register = 02h

After Instruction
BSR Register = 05h

MOVLW Move Literal to W

Syntax: MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → W
Status Affected: None
Encoding:
| 0000 | 1110 | kkkk | kkkk |
Description: The eight-bit literal ‘k’ is loaded into W.
Words: 1
Cycles: 1

Q Cycle Activity:

Example:
MOVLW 5Ah
After Instruction
W = 5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (W) → f
Status Affected: None
Encoding:
| 0110 | 111a | ffff | ffff |
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the 256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
Words: 1
Cycles: 1

Q Cycle Activity:

Example:
MOVWF REG, 0
Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh

MULLW Multiply Literal with W

Syntax: MULLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) x k → PRODH:PRODL
Status Affected: None
Encoding:
| 0000 | 1101 | kkkk | kkkk |

Description:
An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is possible in this operation. A zero result is possible but not detected.

Words: 1
Cycles: 1

Q Cycle Activity:

Example: MULLW 0C4h
Before Instruction
W = E2h
PRODH = ?
PRODL = ?
After Instruction
W = E2h
PRODH = ADh
PRODL = 08h

MULWF Multiply W with f

Syntax: MULWF f {,a}
Operands: 0 ≤ f ≤ 255
a ∈ [0,1]
Operation: (W) x (f) → PRODH:PRODL
Status Affected: None
Encoding:
| 0000 | 001a | ffff | ffff |

Description:
An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1
Cycles: 1

Q Cycle Activity:

Example: MULWF REG, 1
Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h

NEGF Negate f

Syntax:
NEGF f {,a}

Operands:
0 ≤ f ≤ 255
a ∈ [0,1]

Operation:
(f̄) + 1 → f

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0110 | 110a | ffff | ffff |

Description:
Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]

NOP No Operation

Syntax:
NOP

Operands:
None

Operation:
No operation

Status Affected:
None

Encoding:
| 0000 1111 | 0000 xxxx | 0000 xxxx | 0000 xxxx |

Description:
No operation.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
None.

POP

Pop Top of Return Stack

Syntax:
POP

Operands:
None

Operation:
(TOS) → bit bucket

Status Affected:
None

Encoding:
| 0000 | 0000 | 0000 | 0110 |

Description:
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:

POP GOTO NEW

Before Instruction

TOS = 0031A2h Stack (1 level down) = 014332h

After Instruction

TOS = 014332h PC = NEW

PUSH

Push Top of Return Stack

Syntax:
PUSH

Operands:
None

Operation:
(PC + 2) → TOS

Status Affected:
None

Encoding:
| 0000 | 0000 | 0000 | 0101 |

Description:
The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack.
This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:

PUSH

Before Instruction

TOS = 345Ah PC = 0124h

After Instruction

PC = 0126h TOS = 0126h Stack (1 level down) = 345Ah

RCALL Relative Call

Syntax: RCALL n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 → TOS,
(PC) + 2 + 2n → PC

Status Affected: None

Encoding: | 1101 | 1nnn | nnnn | nnnn |

Description: Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Example: HERE RCALL Jump

Before Instruction PC = Address (HERE)

After Instruction PC = Address (Jump) TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are affected by a MCLR Reset.

Status Affected: All

Encoding: | 0000 | 0000 | 1111 | 1111 |

Description: This instruction provides a way to execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Example: RESET

After Instruction Registers = Reset Value Flags* = Reset Value

RETFIE Return from Interrupt

Syntax:
RETFIE {s}

Operands:
s ∈ [0,1]

Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(WS) → W,
(STATUS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged

Status Affected:
GIE/GIEH, PEIE/GIEL.

Encoding:
| 0000 | 0000 | 0001 | 000s |

Description:
Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers WS, STATUS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default).

Words:
1

Cycles:
2

Q Cycle Activity:

Example:
RETFIE 1

After Interrupt
PC = TOS
W = WS
BSR = BSRS
STATUS = STATUS
GIE/GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax:
RETLW k

Operands:
0 ≤ k ≤ 255

Operation:
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged

Status Affected:
None

Encoding:
| 0000 | 1100 | kkkk | kkkk |

Description:
W is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged.

Words:
1

Cycles:
2

Q Cycle Activity:

Example:

CALL TABLE ; W contains table ; offset value ; W now has ; table value : TABLE ADDWF PCL ; W = offset RETLW k0 ; Begin table RETLW k1 ; : : RETLW kn ; End of table

Before Instruction W = 07h

After Instruction W = value of kn

RETURN Return from Subroutine

Syntax:
RETURN {s}

Operands:
s ∈ [0,1]

Operation:
(TOS) → PC;
if s = 1,
(WS) → W,
(STATUS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged

Status Affected:
None

Encoding:
| 0000 | 0000 | 0001 | 001s |

Description:
Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers WS, STATUS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default).

Words:
1

Cycles:
2

Q Cycle Activity:

Example:
RETURN

After Instruction:
PC = TOS

RLCF Rotate Left f through Carry

Syntax:
RLCF f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>

Status Affected:
C, N, Z

Encoding:
| 0011 | 01da | ffff | ffff |

Description:
The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
RLCF REG, 0, 0

Before Instruction
REG = 1110 0110
C = 0

After Instruction
REG = 1110 0110
W = 1100 1100
C = 1

RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands:

• 0 ≤ f ≤ 255
• d ∈ [0,1]
• a ∈ [0,1]

Operation:

• (f) → dest<n + 1>,
• (f<7>) → dest<0>

Status Affected: N, Z

Encoding: | 0100 | 01da | ffff | ffff |

Description: The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example: RLNCF REG, 1, 0

Before Instruction REG = 1010 1011

After Instruction REG = 0101 0111

RRCF Rotate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands:

• 0 ≤ f ≤ 255
• d ∈ [0,1]
• a ∈ [0,1]

Operation:

• (f) → dest<n – 1>,
• (f<0>) → C,
• (C) → dest<7>

Status Affected: C, N, Z

Encoding: | 0011 | 00da | ffff | ffff |

Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example: RRCF REG, 0, 0

Before Instruction REG = 1110 0110 C = 0

After Instruction REG = 1110 0110 W = 0111 0011 C = 0

RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands:

• 0 ≤ f ≤ 255
• d ∈ [0,1]
• a ∈ [0,1]

Operation:

• (f) → dest<n – 1>,
• (f<0>) → dest<7>

Status Affected: N, Z

Encoding: | 0100 | 00da | ffff | ffff |

Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ is ‘1’, then the bank will be selected as per the BSR value (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example 1: RRNCF REG, 1, 0

Before Instruction REG = 1101 0111

After Instruction REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction W = ? REG = 1101 0111

After Instruction W = 1110 1011 REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands:

• 0 ≤ f ≤ 255
• a ∈ [0,1]

Operation: FFh → f

Status Affected: None

Encoding: | 0110 | 100a | ffff | ffff |

Description: The contents of the specified register are set to FFh. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example: SETF REG, 1

Before Instruction REG = 5Ah

After Instruction REG = FFh

SLEEP

Enter Sleep mode

Syntax:
SLEEP

Operands:
None

Operation:
00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD

Status Affected:
TO, PD

Encoding:
| 0000 | 0000 | 0000 | 0011 |

Description:
The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
The processor is put into Sleep mode with the oscillator stopped.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
SLEEP

Before Instruction
TO = ?
PD = ?

After Instruction
TO = 1†
PD = 0

† If WDT causes wake-up, this bit is cleared.

SUBFWB

Subtract f from W with Borrow

Syntax:
SUBFWB f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(W) – (f) – (C) → dest

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0101 | 01da | ffff | ffff |

Description:
Subtract register ‘f’ and Carry flag (borrow) from W (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example 1:
SUBFWB REG, 1, 0

Before Instruction
REG = 3
W = 2
C = 1

After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative

Example 2:
SUBFWB REG, 0, 0

Before Instruction
REG = 2
W = 5
C = 1

After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive

Example 3:
SUBFWB REG, 1, 0

Before Instruction
REG = 1
W = 2
C = 0

After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0

SUBLW Subtract W from Literal

Syntax: SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k – (W) → W
Status Affected: N, OV, C, DC, Z
Encoding:

Description
W is subtracted from the eight-bit literal ‘k’. The result is placed in W.

Words: 1
Cycles: 1

Q Cycle Activity:

Example 1: SUBLW 02h

Before Instruction
W = 01h
C = ?

After Instruction
W = 01h
C = 1 ; result is positive
Z = 0
N = 0

Example 2: SUBLW 02h

Before Instruction
W = 02h
C = ?

After Instruction
W = 00h
C = 1 ; result is zero
Z = 1
N = 0

Example 3: SUBLW 02h

Before Instruction
W = 03h
C = ?

After Instruction
W = FFh ; (2’s complement)
C = 0 ; result is negative
Z = 0
N = 1

SUBWF Subtract W from f

Syntax: SUBWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation: (f) – (W) → dest
Status Affected: N, OV, C, DC, Z
Encoding:

Description:
Subtract W from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1
Cycles: 1

Q Cycle Activity:

Example 1: SUBWF REG, 1, 0

Before Instruction
REG = 3
W = 2
C = ?

After Instruction
REG = 1
W = 2
C = 1 ; result is positive
Z = 0
N = 0

Example 2: SUBWF REG, 0, 0

Before Instruction
REG = 2
W = 2
C = ?

After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0

Example 3: SUBWF REG, 1, 0

Before Instruction
REG = 1
W = 2
C = ?

After Instruction
REG = FFh ;(2’s complement)
W = 2
C = 0 ; result is negative
Z = 0
N = 1

SUBWFB Subtract W from f with Borrow

Syntax:
SUBWFB f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) – (W) – (C̅) → dest

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0101 | 10da | ffff | ffff |

Description:
Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example 1:
SUBWFB REG, 1, 0

Before Instruction
REG = 19h (0001 1001)
W = 0Dh (0000 1101)
C = 1

After Instruction
REG = 0Ch (0000 1011)
W = 0Dh (0000 1101)
C = 1
Z = 0
N = 0 ; result is positive

Example 2:
SUBWFB REG, 0, 0

Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0

After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0

Example 3:
SUBWFB REG, 1, 0

Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1110)
C = 1

After Instruction
REG = F5h (1111 0100) ; [2’s comp]
W = 0Eh (0000 1110)
C = 0
Z = 0
N = 1 ; result is negative

SWAPF Swap f

Syntax:
SWAPF f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f<3:0>) → dest<7:4>,
(f<7:4>) → dest<3:0>

Status Affected:
None

Encoding:
| 0011 | 10da | ffff | ffff |

Description:
The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
SWAPF REG, 1, 0

Before Instruction
REG = 53h

After Instruction
REG = 35h

TBLRD Table Read

Syntax: TBLRD (*; *+; -; +)

Operands: None

Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD -, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT

Status Affected: None

Encoding:

Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range.

TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word

The TBLRD instruction can modify the value of TBLPTR as follows:

• no change
• post-increment
• post-decrement
• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction TABLAT = 55h TBLPTR = 00A356h MEMORY (00A356h) = 34h

After Instruction TABLAT = 34h TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before Instruction TABLAT = AAh TBLPTR = 01A357h MEMORY (01A357h) = 12h MEMORY (01A358h) = 34h

After Instruction TABLAT = 34h TBLPTR = 01A358h

TBLWT Table Write

Syntax: TBLWT (*; *+; -; +)

Operands: None

Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; (TABLAT) → Holding Register

Status Affected: None

Encoding:

Description: This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access.

• TBLPTR[0] = 0: Least Significant Byte of Program Memory Word
• TBLPTR[0] = 1: Most Significant Byte of Program Memory Word

The TBLWT instruction can modify the value of TBLPTR as follows:

• no change
• post-increment
• post-decrement
• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

• TABLAT = 55h
• TBLPTR = 00A356h
• HOLDING REGISTER (00A356h) = FFh

After Instructions (table write completion)

• TABLAT = 55h
• TBLPTR = 00A357h
• HOLDING REGISTER (00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

• TABLAT = 34h
• TBLPTR = 01389Ah
• HOLDING REGISTER (01389Ah) = FFh
• HOLDING REGISTER (01389Bh) = FFh

After Instruction (table write completion)

• TABLAT = 34h
• TBLPTR = 01389Bh
• HOLDING REGISTER (01389Ah) = FFh
• HOLDING REGISTER (01389Bh) = 34h

TSTFSZ Test f, Skip if 0

Syntax: TSTFSZ f {,a}

Operands:

• 0 ≤ f ≤ 255
• a ∈ [0,1]

Operation: skip if f = 0

Status Affected: None

Encoding:

| 0110 | 011a | ffff | ffff |

Description: If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE TSTFSZ CNT, 1 NZERO : ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h, PC = Address (ZERO) If CNT ≠ 00h, PC = Address (NZERO)

XORLW Exclusive OR Literal with W

Syntax: XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → W

Status Affected: N, Z

Encoding:

| 0000 | 1010 | kkkk | kkkk |

Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Example:

XORLW 0AFh

Before Instruction

W = B5h

After Instruction

W = 1Ah

XORWF Exclusive OR W with f

Syntax:
XORWF f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(W) .XOR. (f) → dest

Status Affected:
N, Z

Encoding:
| 0001 | 10da | ffff | ffff |

Description:
Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h

After Instruction
REG = 1Ah
W = B5h

26.2 Extended Instruction Set

In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2455/2550/4455/4550 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions.

The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit.

The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution.

The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include:

• Dynamic allocation and deallocation of software stack space when entering and leaving subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software stack

A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 26-1 (page 314) apply to both the standard and extended PIC18 instruction sets.

Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler.

26.2.1 EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets (“[]”). This is done to indicate that the argument is used as an index or offset. The MPASM™ Assembler will flag an error if it determines that an index or offset value is not bracketed.

When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 26.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”.

Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces (“{ }”).

TABLE 26-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

26.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k
Operands: 0 ≤ k ≤ 63
f ∈ [0, 1, 2]
Operation: FSR(f) + k → FSR(f)
Status Affected: None
Encoding:

Example: ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h

ADDULNK Add Literal to FSR2 and Return

Syntax: ADDULNK k
Operands: 0 ≤ k ≤ 63
Operation: FSR2 + k → FSR2, (TOS) → PC
Status Affected: None
Encoding:

Example: ADDULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

DS39632E-page 356 © 2009 Microchip Technology Inc.

CALLW Subroutine Call Using WREG

Syntax:
CALLW

Operands:
None

Operation:
(PC + 2) → TOS,
(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU

Status Affected:
None

Encoding:
| 0000 | 0000 | 0001 | 0100 |

Description
First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR.

Words:
1

Cycles:
2

Q Cycle Activity:

Example:

HERE CALLW

Before Instruction

PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h

After Instruction

PC = 001006h TOS = address (HERE + 2) PCLATH = 10h PCLATU = 00h W = 06h

MOVSF Move Indexed to f

Syntax:
MOVSF [zₛ], fₔ

Operands:
0 ≤ zₛ ≤ 127
0 ≤ fₔ ≤ 4095

Operation:
((FSR2) + zₛ) → fₔ

Status Affected:
None

Encoding:

1st word (source)
| 1110 | 1011 | 0zzz | zzzz zₛ |

2nd word (destin.)
| 1111 | ffff | ffff | ffff fₔ |

Description
The contents of the source register are moved to destination register ‘fₔ’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zₛ’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘fₔ’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh).
The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.
If the resultant source address points to an indirect addressing register, the value returned will be 00h.

Words:
2

Cycles:
2

Q Cycle Activity:

Example:

MOVSF [05h], REG2

Before Instruction

FSR2 = 80h Contents of 85h = 33h REG2 = 11h

After Instruction

FSR2 = 80h Contents of 85h = 33h REG2 = 33h

MOVSS Move Indexed to Indexed

Syntax:
MOVSS [zₛ], [zₔ]

Operands:
0 ≤ zₛ ≤ 127
0 ≤ zₔ ≤ 127

Operation:
((FSR2) + zₛ) → ((FSR2) + zₔ)

Status Affected:
None

Encoding:
1st word (source)
1110 1011 1zzz zzzz zₛ
1111 xxxx xzzz zzzz zₔ
2nd word (dest.)

Description
The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘zₛ’ or ‘zₔ’, respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh).
The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.
If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP.

Words:
2

Cycles:
2

Q Cycle Activity:

Example:
MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents of 85h = 33h
Contents of 86h = 11h

After Instruction
FSR2 = 80h
Contents of 85h = 33h
Contents of 86h = 33h

PUSHL Store Literal at FSR2, Decrement FSR2

Syntax:
PUSHL k

Operands:
0 ≤ k ≤ 255

Operation:
k → (FSR2),
FSR2 – 1 → FSR2

Status Affected:
None

Encoding:
1110 1010 kkkk kkkk

Description:
The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by ‘1’ after the operation. This instruction allows users to push values onto a software stack.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
PUSHL 08h

Before Instruction
FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h

After Instruction
FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h

SUBFSR Subtract Literal from FSR

Syntax: SUBFSR f, k
Operands:

• 0 ≤ k ≤ 63
• f ∈ [0, 1, 2]
  Operation: FSRf – k → FSRf
  Status Affected: None
  Encoding:
  | 1110 | 1001 | ffkk | kkkk | | ------ | ------ | ------ | ------ | Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
  Words: 1
  Cycles: 1
  Q Cycle Activity:
  | Q1 | Q2 | Q3 | Q4 | | -------- | ----------------- | -------------- | ------------------ | | Decode | Read register ‘f’ | Process Data | Write to destination |

Example:
SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh

SUBULNK Subtract Literal from FSR2 and Return

Syntax: SUBULNK k
Operands: 0 ≤ k ≤ 63
Operation:
FSR2 – k → FSR2,
(TOS) → PC
Status Affected: None
Encoding:

Example:
SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)

26.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE

Note: Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely.

In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.6.1 “Indexed Addressing with Literal Offset”). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (‘a’ = 0) or in a GPR bank designated by the BSR (‘a’ = 1). When the extended instruction set is enabled and ‘a’ = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument — that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions — may behave differently when the extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 26.2.3.1 “Extended Instruction Syntax with Standard PIC18 Commands”).

Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing.

Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.

26.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands

When the extended instruction set is enabled, the file register argument, ‘f’, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, ‘k’. As already noted, this occurs only when ‘f’ is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets (“[ ]”). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler.

If the index argument is properly bracketed for Indexed Literal Offset Addressing mode, the Access RAM argument is never specified; it will automatically be assumed to be ‘0’. This is in contrast to standard operation (extended instruction set disabled) when ‘a’ is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing.

26.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET

It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set.

Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses.

When porting an application to the PIC18F2455/2550/4455/4550, it is very important to consider the type of code. A large, re-entrant application that is written in ‘C’ and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.

ADDWF

ADD W to Indexed (Indexed Literal Offset mode)

Syntax:
ADDWF [k] {,d}

Operands:
0 ≤ k ≤ 95
d ∈ [0,1]

Operation:
(W) + ((FSR2) + k) → dest

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0010 | 01d0 | kkkk | kkkk |

Description:
The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ADDWF [OFST], 0

Before Instruction
W = 17h
OFST = 2Ch
FSR2 = 0A00h
Contents of 0A2Ch = 20h

After Instruction
W = 37h
Contents of 0A2Ch = 20h

BSF

Bit Set Indexed (Indexed Literal Offset mode)

Syntax:
BSF [k], b

Operands:
0 ≤ f ≤ 95
0 ≤ b ≤ 7

Operation:
1 → ((FSR2) + k)

Status Affected:
None

Encoding:
| 1000 | bbb0 | kkkk | kkkk |

Description:
Bit ‘b’ of the register indicated by FSR2, offset by the value ‘k’, is set.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
BSF [FLAG_OFST], 7

Before Instruction
FLAG_OFST = 0Ah
FSR2 = 0A00h
Contents of 0A0Ah = 55h

After Instruction
Contents of 0A0Ah = D5h

SETF

Set Indexed (Indexed Literal Offset mode)

Syntax:
SETF [k]

Operands:
0 ≤ k ≤ 95

Operation:
FFh → ((FSR2) + k)

Status Affected:
None

Encoding:
| 0110 | 1000 | kkkk | kkkk |

Description:
The contents of the register indicated by FSR2, offset by ‘k’, are set to FFh.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
SETF [OFST]

Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents of 0A2Ch = 00h

After Instruction
Contents of 0A2Ch = FFh

26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS

The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F2455/2550/4455/4550 family of devices. This includes the MPLAB C18 C compiler, MPASM Assembly language and MPLAB Integrated Development Environment (IDE).

When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is ‘0’, disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming.

To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways:

• A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.

DS39632E-page 362 © 2009 Microchip Technology Inc.