MICROCHIP
PIC18F2455/2550/4455/4550
Data Sheet
28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
© 2009 Microchip Technology Inc. DS39632E
Note the following details of the code protection feature on Microchip devices:
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICTail, PIC$^{32}$ logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
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All other trademarks mentioned herein are property of their respective companies.
© 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
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QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
MICROCHIP PIC18F2455/2550/4455/4550
28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:
- USB V2.0 Compliant
- Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
- Supports Control, Interrupt, Isochronous and Bulk Transfers
- Supports up to 32 Endpoints (16 bidirectional)
- 1 Kbyte Dual Access RAM for USB
- On-Chip USB Transceiver with On-Chip Voltage Regulator
- Interface for Off-Chip USB Transceiver
- Streaming Parallel Port (SPP) for USB streaming transfers (40/44-pin devices only)
Power-Managed Modes:
- Run: CPU on, Peripherals on
- Idle: CPU off, Peripherals on
- Sleep: CPU off, Peripherals off
- Idle mode Currents Down to 5.8 µA Typical
- Sleep mode Currents Down to 0.1 µA Typical
- Timer1 Oscillator: 1.1 µA Typical, 32 kHz, 2V
- Watchdog Timer: 2.1 µA Typical
- Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
- Four Crystal modes, including High-Precision PLL for USB
- Two External Clock modes, Up to 48 MHz
- Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz to 8 MHz
- User-tunable to compensate for frequency drift
- Secondary Oscillator using Timer1 @ 32 kHz
- Dual Oscillator Options allow Microcontroller and USB module to Run at Different Clock Speeds
- Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
- High-Current Sink/Source: 25 mA/25 mA
- Three External Interrupts
- Four Timer modules (Timer0 to Timer3)
- Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
- Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
- Enhanced USART module:
- LIN bus support
- Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I²C™ Master and Slave modes
- 10-Bit, Up to 13-Channel Analog-to-Digital Converter (A/D) module with Programmable Acquisition Time
- Dual Analog Comparators with Input Multiplexing
Special Microcontroller Features:
- C Compiler Optimized Architecture with Optional Extended Instruction Set
- 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical
- 1,000,000 Erase/Write Cycle Data EEPROM Memory Typical
- Flash/Data EEPROM Retention: > 40 Years
- Self-Programmable under Software Control
- Priority Levels for Interrupts
- 8 x 8 Single-Cycle Hardware Multiplier
- Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- Programmable Code Protection
- Single-Supply 5V In-Circuit Serial Programming™ (ICSP™) via Two Pins
- In-Circuit Debug (ICD) via Two Pins
- Optional Dedicated ICD/ICSP Port (44-pin, TQFP package only)
- Wide Operating Voltage Range (2.0V to 5.5V)
| Device | Program Memory | Data Memory | I/O | 10-Bit A/D (ch) | CCP/ECCP (PWM) | SPP | MSSP | EUSART | Comparators | Timers 8/16-Bit | |||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Flash (bytes) | # Single-Word Instructions | SRAM (bytes) | EEPROM (bytes) | SPI | Master I²C™ | ||||||||
| PIC18F2455 | 24K | 12288 | 2048 | 256 | 24 | 10 | 2/0 | No | Y | Y | 1 | 2 | 1/3 |
| PIC18F2550 | 32K | 16384 | 2048 | 256 | 24 | 10 | 2/0 | No | Y | Y | 1 | 2 | 1/3 |
| PIC18F4455 | 24K | 12288 | 2048 | 256 | 35 | 13 | 1/1 | Yes | Y | Y | 1 | 2 | 1/3 |
| PIC18F4550 | 32K | 16384 | 2048 | 256 | 35 | 13 | 1/1 | Yes | Y | Y | 1 | 2 | 1/3 |
Pin Diagrams
28-Pin PDIP, SOIC
40-Pin PDIP
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
Pin Diagrams (Continued)
Note 1: RB3 is the alternate pin for CCP2 multiplexing. 2: Special ICPORT features available in select circumstances. See Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for more information.
Table of Contents
- 1.0 Device Overview ........ 7
- 2.0 Oscillator Configurations ........ 23
- 3.0 Power-Managed Modes ........ 35
- 4.0 Reset ........ 45
- 5.0 Memory Organization ........ 59
- 6.0 Flash Program Memory ........ 81
- 7.0 Data EEPROM Memory ........ 91
- 8.0 8 x 8 Hardware Multiplier ........ 97
- 9.0 Interrupts ........ 99
- 10.0 I/O Ports ........ 113
- 11.0 Timer0 Module ........ 127
- 12.0 Timer1 Module ........ 131
- 13.0 Timer2 Module ........ 137
- 14.0 Timer3 Module ........ 139
- 15.0 Capture/Compare/PWM (CCP) Modules ........ 143
- 16.0 Enhanced Capture/Compare/PWM (ECCP) Module ........ 151
- 17.0 Universal Serial Bus (USB) ........ 165
- 18.0 Streaming Parallel Port ........ 191
- 19.0 Master Synchronous Serial Port (MSSP) Module ........ 197
- 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........ 243
- 21.0 10-Bit Analog-to-Digital Converter (A/D) Module ........ 265
- 22.0 Comparator Module ........ 275
- 23.0 Comparator Voltage Reference Module ........ 281
- 24.0 High/Low-Voltage Detect (HLVD) ........ 285
- 25.0 Special Features of the CPU ........ 291
- 26.0 Instruction Set Summary ........ 313
- 27.0 Development Support ........ 363
- 28.0 Electrical Characteristics ........ 367
- 29.0 DC and AC Characteristics Graphs and Tables ........ 407
- 30.0 Packaging Information ........ 409
- Appendix A: Revision History ........ 419
- Appendix B: Device Differences ........ 419
- Appendix C: Conversion Considerations ........ 420
- Appendix D: Migration From Baseline to Enhanced Devices ........ 420
- Appendix E: Migration From Mid-Range to Enhanced Devices ........ 421
- Appendix F: Migration From High-End to Enhanced Devices ........ 421
- Index ........ 423
- The Microchip Web Site ........ 433
- Customer Change Notification Service ........ 433
- Customer Support ........ 433
- Reader Response ........ 434
- PIC18F2455/2550/4455/4550 Product Identification System ........ 435
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Errata
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NOTES:
DS39632E-page 6 © 2009 Microchip Technology Inc.
1.0 DEVICE OVERVIEW
This document contains device-specific information for the following devices:
- PIC18F2455
- PIC18F2550
- PIC18F4455
- PIC18F4550
- PIC18LF2455
- PIC18LF2550
- PIC18LF4455
- PIC18LF4550
This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. In addition to these features, the PIC18F2455/2550/4455/4550 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2455/2550/4455/4550 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include:
- Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%.
- Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4%, of normal operation requirements.
- On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.
- Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 “Electrical Characteristics” for values.
1.1.2 UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2455/2550/4455/4550 family incorporate a fully featured Universal Serial Bus communications module that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. It also incorporates its own on-chip transceiver and 3.3V regulator and supports the use of external transceivers and voltage regulators.
1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F2455/2550/4455/4550 family offer twelve different oscillator options, allowing users a wide range of choices in developing application hardware. These include:
- Four Crystal modes using crystals or ceramic resonators.
- Four External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O).
- An internal oscillator block which provides an 8 MHz clock (±2% accuracy) and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O.
- A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and External Oscillator modes, which allows a wide range of clock speeds from 4 MHz to 48 MHz.
- Asynchronous dual clock operation, allowing the USB module to run from a high-frequency oscillator while the rest of the microcontroller is clocked from an internal low-power oscillator.
Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation:
- Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.
- Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.
1.2 Other Special Features
- Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.
- Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine, located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field.
- Extended Instruction Set: The PIC18F2455/2550/4455/4550 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Literal Offset Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as C.
- Enhanced CCP Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown for disabling PWM outputs on interrupt or other select conditions, and auto-restart to reactivate outputs once the condition has cleared.
- Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. The TX/CK and RX/DT signals can be inverted, eliminating the need for inverting buffers. Other enhancements include Automatic Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement).
- 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead.
- Dedicated ICD/ICSP Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other microcontroller features. Offered as an option in select packages, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.
1.3 Details on Individual Family Members
Devices in the PIC18F2455/2550/4455/4550 family are available in 28-pin and 40/44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in six ways:
- Flash program memory (24 Kbytes for PIC18FX455 devices, 32 Kbytes for PIC18FX550 devices).
- A/D channels (10 for 28-pin devices, 13 for 40/44-pin devices).
- I/O ports (3 bidirectional ports and 1 input only port on 28-pin devices, 5 bidirectional ports on 40/44-pin devices).
- CCP and Enhanced CCP implementation (28-pin devices have two standard CCP modules, 40/44-pin devices have one standard CCP module and one ECCP module).
- Streaming Parallel Port (present only on 40/44-pin devices).
All other features for devices in this family are identical. These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and Table 1-3.
Like all Microchip PIC18 devices, members of the PIC18F2455/2550/4455/4550 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2550), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by “LF” (such as PIC18LF2550), function over an extended VDD range of 2.0V to 5.5V.
TABLE 1-1: DEVICE FEATURES
| Features | PIC18F2455 | PIC18F2550 | PIC18F4455 | PIC18F4550 |
|---|---|---|---|---|
| Operating Frequency | DC – 48 MHz | DC – 48 MHz | DC – 48 MHz | DC – 48 MHz |
| Program Memory (Bytes) | 24576 | 32768 | 24576 | 32768 |
| Program Memory (Instructions) | 12288 | 16384 | 12288 | 16384 |
| Data Memory (Bytes) | 2048 | 2048 | 2048 | 2048 |
| Data EEPROM Memory (Bytes) | 256 | 256 | 256 | 256 |
| Interrupt Sources | 19 | 19 | 20 | 20 |
| I/O Ports | Ports A, B, C, (E) | Ports A, B, C, (E) | Ports A, B, C, D, E | Ports A, B, C, D, E |
| Timers | 4 | 4 | 4 | 4 |
| Capture/Compare/PWM Modules | 2 | 2 | 1 | 1 |
| Enhanced Capture/Compare/PWM Modules | 0 | 0 | 1 | 1 |
| Serial Communications | MSSP, Enhanced USART | MSSP, Enhanced USART | MSSP, Enhanced USART | MSSP, Enhanced USART |
| Universal Serial Bus (USB) Module | 1 | 1 | 1 | 1 |
| Streaming Parallel Port (SPP) | No | No | Yes | Yes |
| 10-Bit Analog-to-Digital Module | 10 Input Channels | 10 Input Channels | 13 Input Channels | 13 Input Channels |
| Comparators | 2 | 2 | 2 | 2 |
| Resets (and Delays) | POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT | POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT | POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT | POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT |
| Programmable Low-Voltage Detect | Yes | Yes | Yes | Yes |
| Programmable Brown-out Reset | Yes | Yes | Yes | Yes |
| Instruction Set | 75 Instructions; 83 with Extended Instruction Set enabled | 75 Instructions; 83 with Extended Instruction Set enabled | 75 Instructions; 83 with Extended Instruction Set enabled | 75 Instructions; 83 with Extended Instruction Set enabled |
| Packages | 28-Pin PDIP 28-Pin SOIC | 28-Pin PDIP 28-Pin SOIC | 40-Pin PDIP 44-Pin QFN 44-Pin TQFP | 40-Pin PDIP 44-Pin QFN 44-Pin TQFP |
FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM
Note 1: RE3 is multiplexed with \overlineMCLR and is only available when the \overlineMCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 3: RB3 is the alternate pin for CCP2 multiplexing.
DS39632E-page 10 © 2009 Microchip Technology Inc.
FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM
Note 1: RE3 is multiplexed with \overlineMCLR and is only available when the \overlineMCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features (44-Pin TQFP Package Only)” for additional information. 4: RB3 is the alternate pin for CCP2 multiplexing.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS
| Pin Name | Pin Number PDIP, SOIC | Pin Type | Buffer Type | Description |
|---|---|---|---|---|
| MCLR/VPP/RE3MCLRVPPRE3 | 1 | IPI | STST | Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.Digital input. |
| OSC1/CLKIOSC1CLKI | 9 | II | AnalogAnalog | Oscillator crystal or external clock input.Oscillator crystal input or external clock source input.External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) |
| OSC2/CLKO/RA6OSC2CLKORA6 | 10 | OOI/O | ——TTL | Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.General purpose I/O pin. |
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I = Input
P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
Note 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number PDIP, SOIC | Pin Type | Buffer Type | Description |
|---|---|---|---|---|
| RA0/AN0RA0AN0 | 2 | I/OI | TTLAnalog | PORTA is a bidirectional I/O port.Digital I/O.Analog input 0. |
| RA1/AN1RA1AN1 | 3 | I/OI | TTLAnalog | Digital I/O.Analog input 1. |
| RA2/AN2/VREF-/CVREFRA2AN2VREF-CVREF | 4 | I/OIIO | TTLAnalogAnalogAnalog | Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output. |
| RA3/AN3/VREF+RA3AN3VREF+ | 5 | I/OII | TTLAnalogAnalog | Digital I/O.Analog input 3.A/D reference voltage (high) input. |
| RA4/T0CKI/C1OUT/RCVRA4T0CKIC1OUTRCV | 6 | I/OIOI | STST—TTL | Digital I/O.Timer0 external clock input.Comparator 1 output.External USB transceiver RCV input. |
| RA5/AN4/SS/HLVDIN/C2OUTRA5AN4SSHLVDINC2OUT | 7 | I/OIIIO | TTLAnalogTTLAnalog— | Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output. |
| RA6 | — | — | — | See the OSC2/CLKO/RA6 pin. |
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I = Input
P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
Note 2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number PDIP, SOIC | Pin Type | Buffer Type | Description |
|---|---|---|---|---|
| RB0/AN12/INT0/FLT0/SDI/SDA | 21 | I/O | TTL | PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. |
| RB0 | I | Analog | Digital I/O. | |
| AN12 | I | ST | Analog input 12. | |
| INT0 | I | ST | External interrupt 0. | |
| FLT0 | I | ST | PWM Fault input (CCP1 module). | |
| SDI | I | ST | SPI data in. | |
| SDA | I/O | ST | I²C™ data I/O. | |
| RB1/AN10/INT1/SCK/SCL | 22 | I/O | TTL | Digital I/O. |
| RB1 | I | Analog | Analog input 10. | |
| AN10 | I | ST | External interrupt 1. | |
| INT1 | I | ST | Synchronous serial clock input/output for SPI mode. | |
| SCK | I/O | ST | Synchronous serial clock input/output for I²C mode. | |
| SCL | I/O | ST | ||
| RB2/AN8/INT2/VMO | 23 | I/O | TTL | Digital I/O. |
| RB2 | I | Analog | Analog input 8. | |
| AN8 | I | ST | External interrupt 2. | |
| INT2 | I | ST | External USB transceiver VMO output. | |
| VMO | O | — | ||
| RB3/AN9/CCP2/VPO | 24 | I/O | TTL | Digital I/O. |
| RB3 | I | Analog | Analog input 9. | |
| AN9 | I | ST | Capture 2 input/Compare 2 output/PWM2 output. | |
| CCP2(1) | I/O | ST | External USB transceiver VPO output. | |
| VPO | O | — | ||
| RB4/AN11/KBI0 | 25 | I/O | TTL | Digital I/O. |
| RB4 | I | Analog | Analog input 11. | |
| AN11 | I | ST | Interrupt-on-change pin. | |
| KBI0 | I | TTL | ||
| RB5/KBI1/PGM | 26 | I/O | TTL | Digital I/O. |
| RB5 | I | TTL | Interrupt-on-change pin. | |
| KBI1 | I | ST | Low-Voltage ICSP™ Programming enable pin. | |
| PGM | I/O | ST | ||
| RB6/KBI2/PGC | 27 | I/O | TTL | Digital I/O. |
| RB6 | I | TTL | Interrupt-on-change pin. | |
| KBI2 | I | ST | In-Circuit Debugger and ICSP programming clock pin. | |
| PGC | I/O | ST | ||
| RB7/KBI3/PGD | 28 | I/O | TTL | Digital I/O. |
| RB7 | I | TTL | Interrupt-on-change pin. | |
| KBI3 | I | ST | In-Circuit Debugger and ICSP programming data pin. | |
| PGD | I/O | ST |
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I = Input
P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number PDIP, SOIC | Pin Type | Buffer Type | Description |
|---|---|---|---|---|
| RC0/T1OSO/T13CKIRC0T1OSOT13CKI | 11 | I/OOI | ST—ST | PORTC is a bidirectional I/O port.Digital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input. |
| RC1/T1OSI/CCP2/UOERC1T1OSICCP2⁽²⁾UOE | 12 | I/OII/OO | STCMOSST— | Digital I/O.Timer1 oscillator input.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output. |
| RC2/CCP1RC2CCP1 | 13 | I/OI/O | STST | Digital I/O.Capture 1 input/Compare 1 output/PWM1 output. |
| RC4/D-/VMRC4D-VM | 15 | II/OI | TTL—TTL | Digital input.USB differential minus line (input/output).External USB transceiver VM input. |
| RC5/D+/VPRC5D+VP | 16 | II/OO | TTL—TTL | Digital input.USB differential plus line (input/output).External USB transceiver VP input. |
| RC6/TX/CKRC6TXCK | 17 | I/OOI/O | ST—ST | Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see RX/DT). |
| RC7/RX/DT/SDORC7RXDTSDO | 18 | I/OII/OO | STSTST— | Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see TX/CK).SPI data out. |
| RE3 | — | — | — | See MCLR/VPP/RE3 pin. |
| VUSB | 14 | P | — | Internal USB 3.3V voltage regulator output, positive supply for internal USB transceiver. |
| VSS | 8, 19 | P | — | Ground reference for logic and I/O pins. |
| VDD | 20 | P | — | Positive supply for logic and I/O pins. |
Legend: TTL = TTL compatible inputST = Schmitt Trigger input with CMOS levelsO = OutputCMOS = CMOS compatible input or outputI = InputP = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| MCLR/VPP/RE3 | 1 | 18 | 18 | I | ST | Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. |
| MCLR | ||||||
| VPP | P | Programming voltage input. | ||||
| RE3 | I | ST | Digital input. | |||
| OSC1/CLKI | 13 | 32 | 30 | I | Analog | Oscillator crystal or external clock input. |
| OSC1 | I | Analog | Oscillator crystal input or external clock source input. | |||
| CLKI | External clock source input. Always associated with pin function OSC1. (See OSC2/CLKO pin.) | |||||
| OSC2/CLKO/RA6 | 14 | 33 | 31 | O | — | Oscillator crystal or clock output. |
| OSC2 | Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. | |||||
| CLKO | O | — | In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. | |||
| RA6 | I/O | TTL | General purpose I/O pin. |
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I = Input
P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| RA0/AN0RA0AN0 | 2 | 19 | 19 | I/OI | TTLAnalog | PORTA is a bidirectional I/O port.Digital I/O.Analog input 0. |
| RA1/AN1RA1AN1 | 3 | 20 | 20 | I/OI | TTLAnalog | Digital I/O.Analog input 1. |
| RA2/AN2/VREF-/CVREFRA2AN2VREF-CVREF | 4 | 21 | 21 | I/OIIO | TTLAnalogAnalogAnalog | Digital I/O.Analog input 2.A/D reference voltage (low) input.Analog comparator reference output. |
| RA3/AN3/VREF+RA3AN3VREF+ | 5 | 22 | 22 | I/OII | TTLAnalogAnalog | Digital I/O.Analog input 3.A/D reference voltage (high) input. |
| RA4/T0CKI/C1OUT/RCVRA4T0CKIC1OUTRCV | 6 | 23 | 23 | I/OIOI | STST—TTL | Digital I/O.Timer0 external clock input.Comparator 1 output.External USB transceiver RCV input. |
| RA5/AN4/SS/HLVDIN/C2OUTRA5AN4SSHLVDINC2OUT | 7 | 24 | 24 | I/OIIIO | TTLAnalogTTLAnalog— | Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.Comparator 2 output. |
| RA6 | — | — | — | — | — | See the OSC2/CLKO/RA6 pin. |
Legend: TTL = TTL compatible inputST = Schmitt Trigger input with CMOS levelsO = OutputCMOS = CMOS compatible input or outputI = InputP = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| RB0/AN12/INT0/FLT0/SDI/SDA | 33 | 9 | 8 | I/O | TTL | PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. |
| RB0 | I/O | TTL | Digital I/O. | |||
| AN12 | I | Analog | Analog input 12. | |||
| INT0 | I | ST | External interrupt 0. | |||
| FLT0 | I | ST | Enhanced PWM Fault input (ECCP1 module). | |||
| SDI | I | ST | SPI data in. | |||
| SDA | I/O | ST | I²C™ data I/O. | |||
| RB1/AN10/INT1/SCK/SCL | 34 | 10 | 9 | I/O | TTL | Digital I/O. |
| RB1 | I/O | TTL | Digital I/O. | |||
| AN10 | I | Analog | Analog input 10. | |||
| INT1 | I | ST | External interrupt 1. | |||
| SCK | I/O | ST | Synchronous serial clock input/output for SPI mode. | |||
| SCL | I/O | ST | Synchronous serial clock input/output for I²C mode. | |||
| RB2/AN8/INT2/VMO | 35 | 11 | 10 | I/O | TTL | Digital I/O. |
| RB2 | I/O | TTL | Digital I/O. | |||
| AN8 | I | Analog | Analog input 8. | |||
| INT2 | I | ST | External interrupt 2. | |||
| VMO | O | — | External USB transceiver VMO output. | |||
| RB3/AN9/CCP2/VPO | 36 | 12 | 11 | I/O | TTL | Digital I/O. |
| RB3 | I/O | TTL | Digital I/O. | |||
| AN9 | I | Analog | Analog input 9. | |||
| CCP2(1) | I/O | ST | Capture 2 input/Compare 2 output/PWM2 output. | |||
| VPO | O | — | External USB transceiver VPO output. | |||
| RB4/AN11/KBI0/CSSPP | 37 | 14 | 14 | I/O | TTL | Digital I/O. |
| RB4 | I/O | TTL | Digital I/O. | |||
| AN11 | I | Analog | Analog input 11. | |||
| KBI0 | I | TTL | Interrupt-on-change pin. | |||
| CSSPP | O | — | SPP chip select control output. | |||
| RB5/KBI1/PGM | 38 | 15 | 15 | I/O | TTL | Digital I/O. |
| RB5 | I/O | TTL | Digital I/O. | |||
| KBI1 | I | TTL | Interrupt-on-change pin. | |||
| PGM | I/O | ST | Low-Voltage ICSP™ Programming enable pin. | |||
| RB6/KBI2/PGC | 39 | 16 | 16 | I/O | TTL | Digital I/O. |
| RB6 | I/O | TTL | Digital I/O. | |||
| KBI2 | I | TTL | Interrupt-on-change pin. | |||
| PGC | I/O | ST | In-Circuit Debugger and ICSP programming clock pin. | |||
| RB7/KBI3/PGD | 40 | 17 | 17 | I/O | TTL | Digital I/O. |
| RB7 | I/O | TTL | Digital I/O. | |||
| KBI3 | I | TTL | Interrupt-on-change pin. | |||
| PGD | I/O | ST | In-Circuit Debugger and ICSP programming data pin. |
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I = Input
P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| RC0/T1OSO/T13CKIRC0T1OSOT13CKI | 15 | 34 | 32 | I/OOI | ST—ST | PORTC is a bidirectional I/O port.Digital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input. |
| RC1/T1OSI/CCP2/UOERC1T1OSICCP2(2)UOE | 16 | 35 | 35 | I/OII/OO | STCMOSST— | Digital I/O.Timer1 oscillator input.Capture 2 input/Compare 2 output/PWM2 output.External USB transceiver OE output. |
| RC2/CCP1/P1ARC2CCP1P1A | 17 | 36 | 36 | I/OI/OO | STSTTTL | Digital I/O.Capture 1 input/Compare 1 output/PWM1 output.Enhanced CCP1 PWM output, channel A. |
| RC4/D-/VMRC4D-VM | 23 | 42 | 42 | II/OI | TTL—TTL | Digital input.USB differential minus line (input/output).External USB transceiver VM input. |
| RC5/D+/VPRC5D+VP | 24 | 43 | 43 | II/OI | TTL—TTL | Digital input.USB differential plus line (input/output).External USB transceiver VP input. |
| RC6/TX/CKRC6TXCK | 25 | 44 | 44 | I/OOI/O | ST—ST | Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see RX/DT). |
| RC7/RX/DT/SDORC7RXDTSDO | 26 | 1 | 1 | I/OII/OO | STSTST— | Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see TX/CK).SPI data out. |
Legend: TTL = TTL compatible inputST = Schmitt Trigger input with CMOS levelsO = OutputCMOS = CMOS compatible input or outputI = InputP = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| RD0/SPP0RD0SPP0 | 19 | 38 | 38 | I/OI/O | STTTL | PORTD is a bidirectional I/O port or a Streaming Parallel Port (SPP). These pins have TTL input buffers when the SPP module is enabled.Digital I/O.Streaming Parallel Port data. |
| RD1/SPP1RD1SPP1 | 20 | 39 | 39 | I/OI/O | STTTL | Digital I/O.Streaming Parallel Port data. |
| RD2/SPP2RD2SPP2 | 21 | 40 | 40 | I/OI/O | STTTL | Digital I/O.Streaming Parallel Port data. |
| RD3/SPP3RD3SPP3 | 22 | 41 | 41 | I/OI/O | STTTL | Digital I/O.Streaming Parallel Port data. |
| RD4/SPP4RD4SPP4 | 27 | 2 | 2 | I/OI/O | STTTL | Digital I/O.Streaming Parallel Port data. |
| RD5/SPP5/P1BRD5SPP5P1B | 28 | 3 | 3 | I/OI/OO | STTTL— | Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel B. |
| RD6/SPP6/P1CRD6SPP6P1C | 29 | 4 | 4 | I/OI/OO | STTTL— | Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel C. |
| RD7/SPP7/P1DRD7SPP7P1D | 30 | 5 | 5 | I/OI/OO | STTTL— | Digital I/O.Streaming Parallel Port data.Enhanced CCP1 PWM output, channel D. |
Legend: TTL = TTL compatible inputST = Schmitt Trigger input with CMOS levelsO = OutputCMOS = CMOS compatible input or outputI = InputP = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39632E-page 20 © 2009 Microchip Technology Inc.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
| Pin Name | Pin Number | Pin Type | Buffer Type | Description | ||
|---|---|---|---|---|---|---|
| PDIP | QFN | TQFP | ||||
| RE0/AN5/CK1SPPRE0AN5CK1SPP | 8 | 25 | 25 | I/OIO | STAnalog— | PORTE is a bidirectional I/O port.Digital I/O.Analog input 5.SPP clock 1 output. |
| RE1/AN6/CK2SPPRE1AN6CK2SPP | 9 | 26 | 26 | I/OIO | STAnalog— | Digital I/O.Analog input 6.SPP clock 2 output. |
| RE2/AN7/OESPPRE2AN7OESPP | 10 | 27 | 27 | I/OIO | STAnalog— | Digital I/O.Analog input 7.SPP output enable output. |
| RE3 | — | — | — | — | — | See MCLR/VPP/RE3 pin. |
| VSS | 12, 31 | 6, 30, 31 | 6, 29 | P | — | Ground reference for logic and I/O pins. |
| VDD | 11, 32 | 7, 8, 28, 29 | 7, 28 | P | — | Positive supply for logic and I/O pins. |
| VUSB | 18 | 37 | 37 | P | — | Internal USB 3.3V voltage regulator output, positive supply for the USB transceiver. |
| NC/ICCK/ICPGC(3)ICCKICPGC | — | — | 12 | I/OI/O | STST | No Connect or dedicated ICD/ICSP™ port clock.In-Circuit Debugger clock.ICSP programming clock. |
| NC/ICDT/ICPGD(3)ICDTICPGD | — | — | 13 | I/OI/O | STST | No Connect or dedicated ICD/ICSP port clock.In-Circuit Debugger data.ICSP programming data. |
| NC/ICRST/ICVPP(3)ICRSTICVPP | — | — | 33 | IP | —— | No Connect or dedicated ICD/ICSP port Reset.Master Clear (Reset) input.Programming voltage input. |
| NC/ICPORTS(3)ICPORTS | — | — | 34 | P | — | No Connect or 28-pin device emulation.Enable 28-pin device emulation when connected to VSS. |
| NC | — | 13 | — | — | — | No Connect. |
Legend: TTL = TTL compatible inputST = Schmitt Trigger input with CMOS levelsO = OutputCMOS = CMOS compatible input or outputI = InputP = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.2: Default assignment for CCP2 when CCP2MX Configuration bit is set.3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
NOTES:
DS39632E-page 22 © 2009 Microchip Technology Inc.