Microchip PIC18 datasheet: 26.0 Instruction set summary

26.0 INSTRUCTION SET SUMMARY

PIC18F2455/2550/4455/4550 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section.

26.1 Standard Instruction Set

The standard PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits) but there are four instructions that require two program memory locations.

Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped into four basic categories:

• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations

The PIC18 instruction set summary in Table 26-2 lists byte-oriented, bit-oriented, literal and control operations. Table 26-1 shows the opcode field descriptions.

Most byte-oriented instructions have three operands:

1. The file register (specified by 'f')
2. The destination of the result (specified by 'd')
3. The accessed memory (specified by 'a')

The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator 'd' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by 'f')
2. The bit in the file register (specified by 'b')
3. The accessed memory (specified by 'a')

The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located.

The literal instructions may use some of the following operands:

• A literal value to be loaded into a file register (specified by 'k')
• The desired FSR register to load the literal value into (specified by 'f')
• No operand required (specified by '—')

The control instructions may use some of the following operands:

• A program memory address (specified by 'n')
• The mode of the CALL or RETURN instructions (specified by 's')
• The mode of the table read and table write instructions (specified by 'm')
• No operand required (specified by '—')

All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSBs are '1's. If this second word is executed as an instruction (by itself), it will execute as a NOP.

All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP.

The double-word instructions execute in two instruction cycles.

One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs. Two-word branch instructions (if true) would take 3 µs.

Figure 26-1 shows the general formats that the instructions can have. All examples use the convention 'nnh' to represent a hexadecimal number.

The instruction set summary, shown in Table 26-2, lists the standard instructions recognized by the Microchip MPASM™ Assembler.

Section 26.1.1 "Standard Instruction Set" provides a description of each instruction.

TABLE 26-1: OPCODE FIELD DESCRIPTIONS

FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

Example Instruction ADDWF MYREG, W, B

\begin{tabular}{|l|l|l|l|} \hline

• \multicolumn{4}{l}{15 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ 10 \quad 9 \quad 8 \quad 7 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ 0} \ \hline OPCODE & d & a & f (FILE #) \ \hline \end{tabular}

d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address

Byte to Byte move operations (2-word)

Example Instruction MOVFF MYREG1, MYREG2

\begin{tabular}{|l|l|} \hline

• \multicolumn{2}{l}{15 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........

TABLE 26-2: PIC18FXXXX INSTRUCTION SET

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.

26.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W

Syntax:
ADDLW k

Operands:
0 ≤ k ≤ 255

Operation:
(W) + k → W

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0000 | 1111 | kkkk | kkkk |

Description:
The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ADDLW 15h

Before Instruction
W = 10h

After Instruction
W = 25h

ADDWF ADD W to f

Syntax:
ADDWF f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(W) + (f) → dest

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0010 | 01da | ffff | ffff |

Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h

After Instruction
W = 0D9h
REG = 0C2h

Note: All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

ADDWFC

ADD W and Carry bit to f

Syntax:
ADDWFC f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(W) + (f) + (C) → dest

Status Affected:
N, OV, C, DC, Z

Encoding:
| 0010 | 00da | ffff | ffff |

Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ADDWFC REG, 0, 1

Before Instruction
Carry bit = 1
REG = 02h
W = 4Dh

After Instruction
Carry bit = 0
REG = 02h
W = 50h

ANDLW

AND Literal with W

Syntax:
ANDLW k

Operands:
0 ≤ k ≤ 255

Operation:
(W) .AND. k → W

Status Affected:
N, Z

Encoding:
| 0000 | 1011 | kkkk | kkkk |

Description:
The contents of W are ANDed with the 8-bit literal ‘k’. The result is placed in W.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ANDLW 05Fh

Before Instruction
W = A3h

After Instruction
W = 03h

ANDWF — AND W with f

Syntax:
ANDWF f{,d{,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(W) .AND. (f) → dest

Status Affected:
N, Z

Encoding:
| 0001 | 01da | ffff | ffff |

Description:
The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
ANDWF REG, 0, 0

Before Instruction
W = 17h
REG = C2h

After Instruction
W = 02h
REG = C2h

BC — Branch if Carry

Syntax:
BC n

Operands:
-128 ≤ n ≤ 127

Operation:
if Carry bit is ‘1’,
(PC) + 2 + 2n → PC

Status Affected:
None

Encoding:
| 1110 | 0010 | nnnn | nnnn |

Description:
If the Carry bit is ‘1’, then the program will branch.
The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:
1

Cycles:
1(2)

Q Cycle Activity:

If Jump:

If No Jump:

Example:
HERE BC 5

Before Instruction
PC = address (HERE)

After Instruction
If Carry = 1;
PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)

BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands:

• 0 ≤ f ≤ 255
• 0 ≤ b ≤ 7
• a ∈ [0,1]

Operation: 0 → f

Status Affected: None

Encoding:

| 1001 | bbb a | ffff | ffff |

Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example: BCF FLAG_REG, 7, 0 Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128 ≤ n ≤ 127

Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC

Status Affected: None

Encoding:

| 1110 | 0110 | nnnn | nnnn |

Description: If the Negative bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity: If Jump:

If No Jump:

Example: HERE BN Jump Before Instruction PC = address (HERE) After Instruction If Negative = 1; PC = address (Jump) If Negative = 0; PC = address (HERE + 2)

BNC Branch if Not Carry

Syntax: BNC n
Operands: -128 ≤ n ≤ 127
Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC
Status Affected: None
Encoding:
| 1110 | 0011 | nnnn | nnnn |
Description: If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:

Example:
HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0; PC = address (Jump)
If Carry = 1; PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n
Operands: -128 ≤ n ≤ 127
Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC
Status Affected: None
Encoding:
| 1110 | 0111 | nnnn | nnnn |
Description: If the Negative bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:

Example:
HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 0; PC = address (Jump)
If Negative = 1; PC = address (HERE + 2)

BNOV Branch if Not Overflow

Syntax:
BNOV n

Operands:
-128 ≤ n ≤ 127

Operation:
if Overflow bit is ‘0’,
(PC) + 2 + 2n → PC

Status Affected:
None

Encoding:
| 1110 | 0101 | nnnn | nnnn |

Description:
If the Overflow bit is ‘0’, then the program will branch.
The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:
1

Cycles:
1(2)

Q Cycle Activity:
If Jump:

If No Jump:

Example:
HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax:
BNZ n

Operands:
-128 ≤ n ≤ 127

Operation:
if Zero bit is ‘0’,
(PC) + 2 + 2n → PC

Status Affected:
None

Encoding:
| 1110 | 0001 | nnnn | nnnn |

Description:
If the Zero bit is ‘0’, then the program will branch.
The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:
1

Cycles:
1(2)

Q Cycle Activity:
If Jump:

If No Jump:

Example:
HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)

BRA Unconditional Branch

Syntax:
BRA n

Operands:
-1024 ≤ n ≤ 1023

Operation:
(PC) + 2 + 2n → PC

Status Affected:
None

Encoding:
| 1101 | 0nnn | nnnn | nnnn |

Description:
Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.

Words:
1

Cycles:
2

Q Cycle Activity:

Example:
HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)

BSF Bit Set f

Syntax:
BSF f, b {,a}

Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]

Operation:
1 → f

Status Affected:
None

Encoding:
| 1000 | bbb a | ffff | ffff |

Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah

BTFSC Bit Test File, Skip if Clear

Syntax:
BTFSC f, b {,a}

Operands:
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]

Operation:
skip if (f) = 0

Status Affected:
None

Encoding:
| 1011 | bbb a | ffff | ffff |

Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:
HERE BTFSC FLAG, 1, 0
FALSE :
TRUE :

Before Instruction
PC = address (HERE)

After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax:
BTFSS f, b {,a}

Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]

Operation:
skip if (f) = 1

Status Affected:
None

Encoding:
| 1010 | bbb a | ffff | ffff |

Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:
HERE BTFSS FLAG, 1, 0
FALSE :
TRUE :

Before Instruction
PC = address (HERE)

After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)

BTG Bit Toggle f

Syntax:
BTG f, b {,a}

Operands:
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]

Operation:
(f) → f

Status Affected:
None

Encoding:
| 0111 | bbba | ffff | ffff |

Description:
Bit ‘b’ in data memory location ‘f’ is inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
BTG PORTC, 4, 0

Before Instruction:
PORTC = 0111 0101 [75h]

After Instruction:
PORTC = 0110 0101 [65h]

BOV Branch if Overflow

Syntax:
BOV n

Operands:
-128 ≤ n ≤ 127

Operation:
if Overflow bit is ‘1’,
(PC) + 2 + 2n → PC

Status Affected:
None

Encoding:
| 1110 | 0100 | nnnn | nnnn |

Description:
If the Overflow bit is ‘1’, then the program will branch.
The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction.

Words:
1

Cycles:
1(2)

Q Cycle Activity:
If Jump:

If No Jump:

Example:
HERE BOV Jump

Before Instruction
PC = address (HERE)

After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)

BZ Branch if Zero Syntax: BZ n Operands: -128 ≤ n ≤ 127 Operation: if Zero bit is '1', (PC) + 2 + 2n → PC Status Affected: None Encoding: 1110 0000 nnnn nnnn Description: If the Zero bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump:

\begin{tabular}{|l|l|l|l|} \hline Q1 & Q2 & Q3 & Q4 \ \hline Decode & Read literal 'n' & Process Data & Write to PC \ \hline No operation & No operation & No operation & No operation \ \hline \end{tabular} If No Jump:

\begin{tabular}{|l|l|l|l|} \hline Q1 & Q2 & Q3 & Q4 \ \hline Decode & Read literal 'n' & Process Data & No operation \ \hline \end{tabular} Example: HERE BZ Jump Before Instruction PC = address (HERE) After Instruction If Zero = 1; PC = address (Jump) If Zero = 0; PC = address (HERE + 2)

CALL Subroutine Call Syntax: CALL k,{s} Operands: 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1st word (k<7:0>) 1110 110s k$_7$kkk kkkk$0$ 2nd word(k<19:8>) 1111 k${19}$kkk kkkk kkkk$_8$ Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If 's' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then, the 20-bit value 'k' is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity:

\begin{tabular}{|l|l|l|l|} \hline Q1 & Q2 & Q3 & Q4 \ \hline Decode & Read literal 'k'<7:0>, & Push PC to stack & Read literal 'k'<19:8>, Write to PC \ \hline No operation & No operation & No operation & No operation \ \hline \end{tabular} Example: HERE CALL THERE, 1 Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 4) WS = W BSRS = BSR STATUSS = STATUS

DS39632E-page 328 © 2009 Microchip Technology Inc.

CLRF Clear f

Syntax:
CLRF f {,a}

Operands:
0 ≤ f ≤ 255
a ∈ [0,1]

Operation:
000h → f,
1 → Z

Status Affected:
Z

Encoding:
| 0110 | 101a | ffff | ffff |

Description:
Clears the contents of the specified register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
CLRF FLAG_REG, 1

Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax:
CLRWDT

Operands:
None

Operation:
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD

Status Affected:
TO, PD

Encoding:
| 0000 | 0000 | 0000 | 0100 |

Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
CLRWDT

Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO = 1
PD = 1

COMF Complement f

Syntax: COMF f {,d {,a}}

Operands:

• 0 ≤ f ≤ 255
• d ∈ [0,1]
• a ∈ [0,1]

Operation: (f̄) → dest

Status Affected: N, Z

Encoding:

| 0001 | 11da | ffff | ffff |

Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example:

COMF REG, 0, 0

Before Instruction REG = 13h

After Instruction REG = 13h W = ECh

CPFSEQ Compare f with W, Skip if f = W

Syntax: CPFSEQ f {,a}

Operands:

• 0 ≤ f ≤ 255
• a ∈ [0,1]

Operation: (f) – (W), skip if (f) = (W) (unsigned comparison)

Status Affected: None

Encoding:

| 0110 | 001a | ffff | ffff |

Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If ‘f’ = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE CPFSEQ REG, 0 NEQUAL : EQUAL :

Before Instruction PC Address = HERE W = ? REG = ?

After Instruction If REG = W; PC = Address (EQUAL) If REG ≠ W; PC = Address (NEQUAL)

CPFS GT

Compare f with W, Skip if f > W

Syntax:
CPFS GT f {,a}

Operands:
0 ≤ f ≤ 255
a ∈ [0,1]

Operation:
(f) – (W),
skip if (f) > (W)
(unsigned comparison)

Status Affected:
None

Encoding:
| 0110 | 010a | ffff | ffff |

Description:
Compares the contents of data memory location ‘f’ to the contents of the W by performing an unsigned subtraction.
If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE CPFS GT REG, 0 NGREATER : GREATER :

Before Instruction

PC = Address (HERE) W = ?

After Instruction

If REG > W; PC = Address (GREATER) If REG ≤ W; PC = Address (NGREATER)

CPFS LT

Compare f with W, Skip if f < W

Syntax:
CPFS LT f {,a}

Operands:
0 ≤ f ≤ 255
a ∈ [0,1]

Operation:
(f) – (W),
skip if (f) < (W)
(unsigned comparison)

Status Affected:
None

Encoding:
| 0110 | 000a | ffff | ffff |

Description:
Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction.
If the contents of ‘f’ are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE CPFS LT REG, 1 NLESS : LESS :

Before Instruction

PC = Address (HERE) W = ?

After Instruction

If REG < W; PC = Address (LESS) If REG ≥ W; PC = Address (NLESS)

DAW Decimal Adjust W Register

Syntax: DAW
Operands: None
Operation:
If [W<3:0> > 9] or [DC = 1] then,
(W<3:0>) + 6 → W<3:0>;
else,
(W<3:0>) → W<3:0>;

If [W<7:4> + DC > 9] or [C = 1] then,
(W<7:4>) + 6 + DC → W<7:4>;
else,
(W<7:4>) + DC → W<7:4>

Status Affected: C
Encoding:
| 0000 | 0000 | 0000 | 0111 |
Description: DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result.
Words: 1
Cycles: 1
Q Cycle Activity:

Example 1: DAW

Before Instruction
W = A5h
C = 0
DC = 0

After Instruction
W = 05h
C = 1
DC = 0

Example 2:

Before Instruction
W = CEh
C = 0
DC = 0

After Instruction
W = 34h
C = 1
DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (f) – 1 → dest
Status Affected: C, DC, N, OV, Z
Encoding:
| 0000 | 01da | ffff | ffff |
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:

Example: DECF CNT, 1, 0

Before Instruction
CNT = 01h
Z = 0

After Instruction
CNT = 00h
Z = 1

DECFSZ Decrement f, Skip if 0

Syntax:
DECFSZ f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) – 1 → dest,
skip if result = 0

Status Affected:
None

Encoding:
| 0010 | 11da | ffff | ffff |

Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE DECFSZ CNT, 1, 1 GOTO LOOP CONTINUE

Before Instruction
PC = Address (HERE)

After Instruction
CNT = CNT – 1
If CNT = 0;
 PC = Address (CONTINUE)
If CNT ≠ 0;
 PC = Address (HERE + 2)

DCFSNZ Decrement f, Skip if Not 0

Syntax:
DCFSNZ f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) – 1 → dest,
skip if result ≠ 0

Status Affected:
None

Encoding:
| 0100 | 11da | ffff | ffff |

Description:
The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE DCFSNZ TEMP, 1, 0 ZERO : NZERO :

Before Instruction
TEMP = ?

After Instruction
TEMP = TEMP – 1,
If TEMP = 0;
 PC = Address (ZERO)
If TEMP ≠ 0;
 PC = Address (NZERO)

GOTO Unconditional Branch

Syntax:
GOTO k

Operands:
0 ≤ k ≤ 1048575

Operation:
k → PC<20:1>

Status Affected:
None

Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)

Description:
GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction.

Words:
2

Cycles:
2

Q Cycle Activity:

Example:
GOTO THERE

After Instruction
PC = Address (THERE)

INCF Increment f

Syntax:
INCF f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) + 1 → dest

Status Affected:
C, DC, N, OV, Z

Encoding:

Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1

Q Cycle Activity:

Example:
INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?

After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1

INCFSZ Increment f, Skip if 0

Syntax:
INCFSZ f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) + 1 → dest,
skip if result = 0

Status Affected:
None

Encoding:
| 0011 | 11da | ffff | ffff |

Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’. (default)
If the result is ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE INCFSZ CNT, 1, 0 NZERO : ZERO :

Before Instruction
PC = Address (HERE)

After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT ≠ 0;
PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax:
INFSNZ f {,d {,a}}

Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]

Operation:
(f) + 1 → dest,
skip if result ≠ 0

Status Affected:
None

Encoding:
| 0100 | 10da | ffff | ffff |

Description:
The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
If the result is not ‘0’, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words:
1

Cycles:
1(2)
Note: 3 cycles if skip and followed by a 2-word instruction.

Q Cycle Activity:

If skip:

If skip and followed by 2-word instruction:

Example:

HERE INFSNZ REG, 1, 0 ZERO : NZERO :

Before Instruction
PC = Address (HERE)

After Instruction
REG = REG + 1
If REG ≠ 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)

IORLW Inclusive OR Literal with W

Syntax: IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → W
Status Affected: N, Z
Encoding:

Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1

Q Cycle Activity:

Example: IORLW 35h
Before Instruction
W = 9Ah
After Instruction
W = BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation: (W) .OR. (f) → dest
Status Affected: N, Z
Encoding:

Description: Inclusive OR W with register ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
Words: 1
Cycles: 1

Q Cycle Activity:

Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h

LFSR Load FSR

Syntax: LFSR f, k

Operands:

• 0 ≤ f ≤ 2
• 0 ≤ k ≤ 4095

Operation: k → FSRf

Status Affected: None

Encoding:

Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Example:

LFSR 2, 3ABh

After Instruction

• FSR2H = 03h
• FSR2L = ABh

MOVF Move f

Syntax: MOVF f{,d{,a}}

Operands:

• 0 ≤ f ≤ 255
• d ∈ [0,1]
• a ∈ [0,1]

Operation: f → dest

Status Affected: N, Z

Encoding:

Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default). Location ‘f’ can be anywhere in the 256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Example:

MOVF REG, 0, 0

Before Instruction

• REG = 22h
• W = FFh

After Instruction

• REG = 22h
• W = 22h