Microchip PIC18 datasheet: 18.0 Streaming parallel port

18.0 STREAMING PARALLEL PORT

Note: The Streaming Parallel Port is only available on 40/44-pin devices.

PIC18F4455/4550 USB devices provide a Streaming Parallel Port as a high-speed interface for moving data to and from an external system. This parallel port operates as a master port, complete with chip select and clock outputs to control the movement of data to slave devices. Data can be channelled either directly to the USB SIE or to the microprocessor core. Figure 18-1 shows a block view of the SPP data path.

FIGURE 18-1: SPP DATA PATH

In addition, the SPP can provide time multiplexed addressing information along with the data by using the second strobe output. Thus, the USB endpoint number can be written in conjunction with the data for that endpoint.

18.1 SPP Configuration

The operation of the SPP is controlled by two registers: SPPCON and SPPCFG. The SPPCON register (Register 18-1) controls the overall operation of the parallel port and determines if it operates under USB or microcontroller control. The SPPCFG register (Register 18-2) controls timing configuration and pin outputs.

18.1.1 ENABLING THE SPP

To enable the SPP, set the SPPEN bit (SPPCON<0>). In addition, the TRIS bits for the corresponding SPP pins must be properly configured. At a minimum:

• Bits TRISD<7:0> must be set (= 1)
• Bits TRISE<2:1> must be cleared (= 0)

If CK1SPP is to be used:

• Bit TRISE<0> must be cleared (= 0)

If CSPP is to be used:

• Bit TRISB<4> must be cleared (= 0)

REGISTER 18-1: SPPCON: SPP CONTROL REGISTER

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’
bit 1 SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
bit 0 SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled

REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7-6
CLKCFG1:CLKCFG0: SPP Clock Configuration bits
1x = CLK1 toggles on read or write of an Odd endpoint address;
  CLK2 toggles on read or write of an Even endpoint address
01 = CLK1 toggles on write; CLK2 toggles on read
00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write

bit 5
CSEN: SPP Chip Select Pin Enable bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port

bit 4
CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port

bit 3-0
WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states
•
•
•
0001 = 2 additional wait states
0000 = 0 additional wait states

18.1.2 CLOCKING DATA

The SPP has four control outputs:

• Two separate clock outputs (CK1SPP and CK2SPP)
• Output enable (OESPP)
• Chip select (CSSPP)

Together, they allow for several different configurations for controlling the flow of data to slave devices. When all control outputs are used, the three main options are:

• CLK1 clocks endpoint address information while CLK2 clocks data
• CLK1 clocks write operations while CLK2 clocks reads
• CLK1 clocks Odd address data while CLK2 clocks Even address data

Additional control options are derived by disabling the CK1SPP and CSSPP outputs. These are enabled or disabled with the CLK1EN and CSEN bits, respectively, located in Register 18-2.

18.1.3 WAIT STATES

The SPP is designed with the capability of adding wait states to read and write operations. This allows access to parallel devices that require extra time for access.

Wait state clocking is based on the data source clock. If the SPP is configured to operate as a USB endpoint, then wait states are based on the USB clock. Likewise, if the SPP is configured to operate from the microcontroller, then wait states are based on the instruction rate (Fosc/4).

The WS3:WS0 bits set the wait states used by the SPP, with a range of no wait states to 30 wait states, in multiples of two. The wait states are added symmetrically to all transactions, with one-half added following each of the two clock cycles normally required for the transaction. Figure 18-3 and Figure 18-4 show signalling examples with 4 wait states added to each transaction.

18.1.4 SPP PULL-UPS

The SPP data lines (SPP<7:0>) are equipped with internal pull-ups for applications that may leave the port in a high-impedance condition. The pull-ups are enabled using the control bit, RDPU (PORTE<7>).

FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND READ DATA (NO WAIT STATES)

Write Address MOVWF SPPEPS

Write Data MOVWF SPPDATA

Read Data MOVF SPPDATA, W

FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)

FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)

18.2 Setup for USB Control

When the SPP is configured for USB operation, data can be clocked directly to and from the USB peripheral without intervention of the microcontroller; thus, no process time is required. Data is clocked into or out from the SPP with endpoint (address) information first, followed by one or more bytes of data, as shown in Figure 18-5. This is ideal for applications that require isochronous, large volume data movement.

The following steps are required to set up the SPP for USB control:

1. Configure the SPP as desired, including wait states and clocks.
2. Set the SPPOWN bit for USB ownership.
3. Set the buffer descriptor starting address (BDnADRL:BDnADRH) to FFFFh.
4. Set the KEN bit (BDnSTAT<5>) so the buffer descriptor is kept indefinitely by the SIE.
5. Set the INCDIS bit (BDnSTAT<4>) to disable automatic buffer address increment.
6. Set the SPPEN bit to enable the module.

Note: If a USB endpoint is configured to use the SPP, the data transfer type of that endpoint must be isochronous only.

18.3 Setup for Microcontroller Control

The SPP can also act as a parallel port for the microcontroller. In this mode, the SPPEPS register (Register 18-3) provides status and address write control. Data is written to and read from the SPPDATA register. When the SPP is owned by the microcontroller, the SPP clock is driven by the instruction clock (Fosc/4).

The following steps are required to set up the SPP for microcontroller operation:

1. Configure the SPP as desired, including wait states and clocks.
2. Clear the SPPOWN bit.
3. Set SPPEN to enable the module.

18.3.1 SPP INTERRUPTS

When owned by the microcontroller core, control can generate an interrupt to notify the application when each read and write operation is completed. The interrupt flag bit is SPPIF (PIR1<7>) and is enabled by the SPPIE bit (PIE1<7>). Like all other microcontroller level interrupts, it can be set to a low or high priority. This is done with the SPPIP bit (IPR1<7>).

18.3.2 WRITING TO THE SPP

Once configured, writing to the SPP is performed by writing to the SPPEPS and SPPDATA registers. If the SPP is configured to clock out endpoint address information with the data, writing to the SPPEPS register initiates the address write cycle. Otherwise, the write is started by writing the data to the SPPDATA register. The SPPBUSY bit indicates the status of the address and the data write cycles.

The following is an example write sequence:

1. Write the 4-bit address to the SPPEPS register. The SPP automatically starts writing the address. If address write is not used, then skip to step 3.
2. Monitor the SPPBUSY bit to determine when the address has been sent. The duration depends on the wait states.
3. Write the data to the SPPDATA register. The SPP automatically starts writing the data.
4. Monitor the SPPBUSY bit to determine when the data has been sent. The duration depends on the wait states.
5. Go back to steps 1 or 3 to write a new address or data.

Note: The SPPBUSY bit should be polled to make certain that successive writes to the SPPEPS or SPPDATA registers do not overrun the wait time due to the wait state setting.

FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP

DS39632E-page 194 © 2009 Microchip Technology Inc.

18.3.3 READING FROM THE SPP

Reading from the SPP involves reading the SPPDATA register. Reading the register the first time initiates the read operation. When the read is finished, indicated by the SPPBUSY bit, the SPPDATA will be loaded with the current data.

The following is an example read sequence:

1. Write the 4-bit address to the SPPEPS register. The SPP automatically starts writing the address. If address write is not used then skip to step 3.
2. Monitor the SPPBUSY bit to determine when the address has been sent. The duration depends on the wait states.
3. Read the data from the SPPDATA register; the data from the previous read operation is returned. The SPP automatically starts the read cycle for the next read.
4. Monitor the SPPBUSY bit to determine when the data has been read. The duration depends on the wait states.
5. Go back to step 3 to read the current byte from the SPP and start the next read cycle.

REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER

bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB) 1 = The last transaction was a read from the SPP 0 = The last transaction was not a read from the SPP

bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB) 1 = The last transaction was a write to the SPP 0 = The last transaction was not a write to the SPP

bit 5 Unimplemented: Read as ‘0’

bit 4 SPPBUSY: SPP Handshaking Override bit 1 = The SPP is busy 0 = The SPP is ready to accept another read or write request

bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits 1111 = Endpoint Address 15 • • • • 0001 0000 = Endpoint Address 0

TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices).

3: These registers and/or bits are unimplemented on 28-pin devices.

19.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE

19.1 Master SSP (MSSP) Module Overview

The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I²C™)
  • Full Master mode
  • Slave mode (with general address call)

The I²C interface supports the following modes in hardware:

• Master mode
• Multi-Master mode
• Slave mode

19.2 Control Registers

The MSSP module has three associated control registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual Configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I²C mode.

Additional details are provided under the individual sections.

19.3 SPI Mode

The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of the SPI are supported. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) – RC7/RX/DT/SDO
• Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA
• Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL

Additionally, a fourth pin may be used when in a Slave mode of operation:

• Slave Select (SS̅) – RA5/AN4/SS̅/HLVDIN/C2OUT

Figure 19-1 shows the block diagram of the MSSP module when operating in SPI mode.

FIGURE 19-1: MSSP BLOCK DIAGRAM (SPI MODE)

Note: Only those pin functions relevant to SPI operation are shown here.

19.3.1 REGISTERS

The MSSP module has four registers for SPI mode operation. These are:

• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly accessible

SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from.

In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.

REGISTER 19-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.

bit 6
CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state

bit 5
D/A: Data/Address bit
Used in I²C mode only.

bit 4
P: Stop bit
Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3
S: Start bit
Used in I²C mode only.

bit 2
R/W: Read/Write Information bit
Used in I²C mode only.

bit 1
UA: Update Address bit
Used in I²C mode only.

bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).

REGISTER 19-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision

bit 6
SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow

bit 5
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins(2)

bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level

bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin(3)
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3)
0011 = SPI Master mode, clock = TMR2 output/2(3,4)
0010 = SPI Master mode, clock = Fosc/64(3)
0001 = SPI Master mode, clock = Fosc/16(3)
0000 = SPI Master mode, clock = Fosc/4(3)

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I²C™ mode only.
4: PR2 = 0x00 is not supported when running the SPI module in TMR2 Output/2 mode.

19.3.2 OPERATION

When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified:

• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data output time)
• Clock Edge (output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)

The MSSP module consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full detect bit, BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully.

The Buffer Full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 19-1 shows the loading of the SSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions.

Note: The SSPBUF register cannot be used with read-modify-write instructions, such as BCF, BTFSC and COMF.

EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER

TransmitSPI: BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous ;transmission). MOVF SSPUF, W ;Perform read, even if the data in SSPUF is not important MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send) MOVWF SSPUF ;Load data to send into transmit buffer

WaitComplete: ;Loop until data has finished transmitting BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete BRA WaitComplete

DS39632E-page 200 © 2009 Microchip Technology Inc.

19.3.3 ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and \overlineSS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows:

• SDI must have TRISB<0> bit set (configure as digital in ADCON1)
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<1> bit cleared
• SCK (Slave mode) must have TRISB<1> bit set (configure as digital in ADCON1)
• \overlineSS must have TRISA<5> bit set (configure as digital in ADCON1)

Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Input functions which will not be used do not need to be configured as digital inputs.

19.3.4 TYPICAL CONNECTION

Figure 19-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission:

• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data

FIGURE 19-2: SPI MASTER/SLAVE CONNECTION

19.3.5 MASTER MODE

The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 19-2) is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This, then, would give waveforms for SPI communication as shown in Figure 19-3, Figure 19-5 and Figure 19-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following:

• Fosc/4 (or Tcy)
• Fosc/16 (or 4 • Tcy)
• Fosc/64 (or 16 • Tcy)
• Timer2 output/2

This allows a maximum data rate (at 48 MHz) of 12.00 Mbps.

When used in Timer2 Output/2 mode, the bit rate can be configured using the PR2 Period register and the Timer2 prescaler. However, writing to SSPBUF does not clear the current TMR2 value in hardware. Depending upon the current value of TMR2 when the user firmware writes to SSPBUF, this can result in an unpredictable MSb bit width, unless the procedure of Example 19-2 is used.

Figure 19-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.

EXAMPLE 19-2: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE

TransmitSPI: BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous ;transmission) MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful BCF T2CON, TMR2ON ;Turn off timer when loading SSPBUF CLRF TMR2 ;Set timer to a known state MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send) MOVWF SSPBUF ;Load data to send into transmit buffer BSF T2CON, TMR2ON ;Start timer to begin transmission

WaitComplete: BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete BRA WaitComplete

FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE)

19.3.6 SLAVE MODE

In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set.

While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device can be configured to wake-up from Sleep.

19.3.7 SLAVE SELECT SYNCHRONIZATION

The \overlineSS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with the \overlineSS pin control enabled (SSPCON1<3:0> = 04h). When the \overlineSS pin is low, transmission and reception are enabled and the SDO pin is driven. When the \overlineSS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application.

Note 1: When the SPI module is in Slave mode with \overlineSS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset if the \overlineSS pin is set to VDD.

2: If the SPI is used in Slave mode with CKE set, then the \overlineSS pin control must be enabled.

When the SPI module resets, the bit counter is forced to '0'. This can be done by either forcing the \overlineSS pin to a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict.

FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM

DS39632E-page 204 © 2009 Microchip Technology Inc.

FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

19.3.8 OPERATION IN POWER-MANAGED MODES

In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted.

In most Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 2.4 “Clock Sources and Oscillator Switching” for additional information.

In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system.

If MSSP interrupts are enabled, they can wake the controller from Sleep mode or one of the Idle modes when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled.

If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device.

19.3.9 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the current transfer.

19.3.10 BUS MODE COMPATIBILITY

Table 19-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.

TABLE 19-1: SPI BUS MODES

There is also an SMP bit which controls when the data is sampled.

TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.

Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.

2: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.

19.4 I²C Mode

The MSSP module in I²C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL
• Serial data (SDA) – RB0/AN12/INT0/FLT0/SDI/SDA

The user must configure these pins as inputs by setting the associated TRIS bits.

FIGURE 19-7: MSSP BLOCK DIAGRAM (I²C™ MODE)

Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions.

19.4.1 REGISTERS

The MSSP module has six registers for I²C operation. These are:

• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly accessible
• MSSP Address Register (SSPADD)

SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I²C mode operation. The SSPCON1 and SSPCON2 registers are readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from.

SSPADD register holds the slave device address when the MSSP is configured in I²C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD act as the Baud Rate Generator reload value.

In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.

REGISTER 19-3: SSPSTAT: MSSP STATUS REGISTER (I²C™ MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs

bit 5
D/Ā: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address

bit 4
P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last

bit 3
S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last

bit 2
R/W̅: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress

bit 1
UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK̅ and Stop bits)
0 = SSPBUF is empty (does not include the ACK̅ and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W̅ bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK̅ bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

REGISTER 19-4: SSPCON1: MSSP CONTROL REGISTER 1 (I²C™ MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I²C conditions were not valid for a transmission to be started (must be cleared in software)
0 = No collision

In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision

In Receive mode (Master or Slave modes):
This is a “don’t care” bit.

bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software)
0 = No overflow

In Transmit mode:
This is a “don’t care” bit in Transmit mode.

bit 5
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins⁽¹⁾
0 = Disables serial port and configures these pins as I/O port pins⁽¹⁾

bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time

In Master mode:
Unused in this mode.

bit 3-0
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111 = I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled⁽²⁾
1110 = I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled⁽²⁾
1011 = I²C Firmware Controlled Master mode (slave Idle)⁽²⁾
1000 = I²C Master mode, clock = Fosc/(4 * (SSPADD + 1))⁽²,³⁾
0111 = I²C Slave mode, 10-bit address⁽²⁾
0110 = I²C Slave mode, 7-bit address⁽²⁾

Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.
Note 2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Note 3: Guideline only; exact baud rate slightly dependent upon circuit conditions, but the highest clock rate should not exceed this formula. SSPADD values of ‘0’ and ‘1’ are not supported.

REGISTER 19-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ MASTER MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
GCEN: General Call Enable bit (Slave mode only)
Unused in Master mode.

bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave

bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge

bit 4
ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware.
0 = Acknowledge sequence Idle

bit 3
RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I²C
0 = Receive Idle

bit 2
PEN: Stop Condition Enable bit(2)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle

bit 1
RSEN: Repeated Start Condition Enable bit(2)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle

bit 0
SEN: Start Condition Enable/Stretch Enable bit(2)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle

Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I²C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

REGISTER 19-6: SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ SLAVE MODE)

Legend:

R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown

bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled

bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.

bit 5-2
ADMSK5:ADMSK2: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled

bit 1
ADMSK1: Slave Address Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SPADD<1> only enabled
0 = Masking of SPADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPADD<1:0> enabled
0 = Masking of SSPADD<1:0> disabled

bit 0
SEN: Stretch Enable bit⁽¹⁾
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1: If the I²C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

19.4.2 OPERATION

The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I²C operation. Four mode selection bits (SSPCON1<3:0>) allow one of the following I²C modes to be selected:

• I²C Master mode, clock
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address) with Start and Stop bit interrupts enabled
• I²C Slave mode (10-bit address) with Start and Stop bit interrupts enabled
• I²C Firmware Controlled Master mode, slave is Idle

Selection of any I²C mode with the SSPEN bit set forces the SCL and SDA pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISC or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.

19.4.3 SLAVE MODE

In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter).

The I²C Slave mode hardware will always generate an interrupt on an address match. Address masking will allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits.

When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register.

Any combination of the following conditions will cause the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), was set before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit, SSPIF, is set. The BF bit is cleared by reading the SSPBUF register, while bit, SSPOV, is cleared through software.

The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I²C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101.

19.4.3.1 Addressing

Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur:

1. The SSPSR register value is loaded into the SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCL pulse.

In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the address. The sequence of events for 10-bit addressing is as follows, with steps 7 through 9 for the slave-transmitter:

1. Receive first (high) byte of address (bits SSPIF, BF and UA (SSPSTAT<1>) are set on address match).
2. Update the SSPADD register with second (low) byte of address (clears bit, UA, and releases the SCL line).
3. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF.
4. Receive second (low) byte of address (bits, SSPIF, BF and UA, are set).
5. Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit, UA.
6. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits, SSPIF and BF, are set).
9. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF.

19.4.3.2 Address Masking

Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see Example 19-3).

The I²C Slave behaves the same way whether address masking is used or not. However, when address masking is used, the I²C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking SSPBUF.

In 7-Bit Address mode, address mask bits ADMASK<5:1> (SSPCON2<5:1>) mask the corresponding address bits in the SSPADD register. For any ADMASK bits that are set (ADMSK = 1), the corresponding address bit is ignored (SSPADD = x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask.

In 10-Bit Address mode, bits ADMASK<5:2> mask the corresponding address bits in the SSPADD register. In addition, ADMASK1 simultaneously masks the two LSbs of the address (SSPADD<1:0>). For any ADMASK bits that are active (ADMSK = 1), the corresponding address bit is ignored (SSPADD = x). Also note that although in 10-Bit Addressing mode, the upper address bits reuse part of the SSPADD register bits, the address mask bits do not interact with those bits. They only affect the lower address bits.

Note 1: ADMASK1 masks the two Least Significant bits of the address.
2: The two Most Significant bits of the address are not affected by address masking.

EXAMPLE 19-3: ADDRESS MASKING EXAMPLES

7-bit addressing:
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh

10-bit addressing:
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh