Field-Programmable Gate Arrays

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Regarding process time calculation

Sir I want to know that how we can calculate time taken by a process or in Xilinx ISE anywhwhere we can see it as we ar...
16 comments posted 15yrs
posted by VARUN_AGR
16 comments posted 15yrs posted by VARUN_AGR

Re: FPGA security, Actel down, now Xilinx too?

> A better metric for FPGA bitstream security, or any security product, > is the cost per breach and/or time per breach...
1 comments posted 15yrs
posted by stephen.craven
1 comments posted 15yrs posted by stephen.craven

die's in different packages

can someone tell me if there is any differences in the die for the following 2 devices in virtex-7 XC7VX415TFFG1158 and...
6 comments posted 15yrs
posted by sharan.basappa
6 comments posted 15yrs posted by sharan.basappa

DVI-decoder clock question

Let say I have two DVI streams - generated by two encoders, those have different video contents but same pixel clock Th...
3 comments posted 15yrs
posted by ccon67
3 comments posted 15yrs posted by ccon67

Bitstream compression

Hey all-- So my experience with the native bitstream compression algorithms provided by the FPGA vendors has been that...
15 comments posted 15yrs
posted by rgaddi
15 comments posted 15yrs posted by rgaddi

image storing into BRAM

dear all, i want to store image from PC to BRAM of an FPGA.i have image 192x96 size. 1) which type of interfacing shoul...
10 comments posted 15yrs
posted by balajigec
10 comments posted 15yrs posted by balajigec

VHDL horror in Xcell 76

There is an utterly horrible VHDL howler on page of 45 of the latest Xcell Journal. Two example codes for a register wi...
7 comments posted 15yrs
posted by robert.ingham
7 comments posted 15yrs posted by robert.ingham

synthesizing

Hi all I want to calculate a simple formula, including multiply and division operands. I use Verilog language to progra...
3 comments posted 15yrs
posted by mahdiyar.sarayloo
3 comments posted 15yrs posted by mahdiyar.sarayloo

About the setup time of BUFGMUX in Spartan6

I'm so confused about the setup time of BUFGMUX. In the datasheet of Spartan6, this spec is defined relatively to risin...
1 comments posted 15yrs
posted by chenjh1984
1 comments posted 15yrs posted by chenjh1984

Speed attained by virtex 6

Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operan...
2 comments posted 15yrs
posted by fpga.dev69
2 comments posted 15yrs posted by fpga.dev69

sdxc

Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay b...
0 comments posted 15yrs
posted by sk3ptic
0 comments posted 15yrs posted by sk3ptic