Field-Programmable Gate Arrays

Pipeline stages of the Multiplier core (ISE Coregen)

Hello friends I can't understand how the Pipeline stages affect the multiplier core? I tested 1 stage and 4 stages. The...

1 comments posted 15yrs

posted by spman_xm

1 comments posted 15yrs posted by spman_xm

die's in different packages

can someone tell me if there is any differences in the die for the following 2 devices in virtex-7 XC7VX415TFFG1158 and...

6 comments posted 15yrs

posted by sharan.basappa

6 comments posted 15yrs posted by sharan.basappa

DVI-decoder clock question

Let say I have two DVI streams - generated by two encoders, those have different video contents but same pixel clock Th...

3 comments posted 15yrs

posted by ccon67

3 comments posted 15yrs posted by ccon67

Bitstream compression

Hey all-- So my experience with the native bitstream compression algorithms provided by the FPGA vendors has been that...

15 comments posted 15yrs

posted by rgaddi

15 comments posted 15yrs posted by rgaddi

image storing into BRAM

dear all, i want to store image from PC to BRAM of an FPGA.i have image 192x96 size. 1) which type of interfacing shoul...

10 comments posted 15yrs

posted by balajigec

10 comments posted 15yrs posted by balajigec

VHDL horror in Xcell 76

There is an utterly horrible VHDL howler on page of 45 of the latest Xcell Journal. Two example codes for a register wi...

7 comments posted 15yrs

posted by robert.ingham

7 comments posted 15yrs posted by robert.ingham

Question on PCI-express verssus Standard PCI performance

Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1...

6 comments posted 15yrs

posted by benjamin.couillard

6 comments posted 15yrs posted by benjamin.couillard

synthesizing

Hi all I want to calculate a simple formula, including multiply and division operands. I use Verilog language to progra...

3 comments posted 15yrs

posted by mahdiyar.sarayloo

3 comments posted 15yrs posted by mahdiyar.sarayloo

About the setup time of BUFGMUX in Spartan6

I'm so confused about the setup time of BUFGMUX. In the datasheet of Spartan6, this spec is defined relatively to risin...

1 comments posted 15yrs

posted by chenjh1984

1 comments posted 15yrs posted by chenjh1984

Post-map simulation: timing violation and delays

Hi all, I am trying to implement a custom counter (with clock and enable inputs); synthesis and behavioral & post-trans...

6 comments posted 15yrs

posted by sd

6 comments posted 15yrs posted by sd

source synchronous DDR bus with non-continuous clock

I'm hoping to get some help/advise on how to design this interface. We're targeting Spartan-6. There=92s a bidirectiona...

8 comments posted 15yrs

posted by mikegulotta

8 comments posted 15yrs posted by mikegulotta

Speed attained by virtex 6

Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operan...

2 comments posted 15yrs

posted by fpga.dev69

2 comments posted 15yrs posted by fpga.dev69

sdxc

Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay b...

0 comments posted 15yrs

posted by sk3ptic

0 comments posted 15yrs posted by sk3ptic

Issues with Soft-Cores

Hello. I'm a little bit tinkering with soft core cpus for fpgas, but I really have serious issues doing so. Thats why I...

7 comments posted 15yrs

posted by andre.zeps

7 comments posted 15yrs posted by andre.zeps

RTL timing issue

Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am...

5 comments posted 15yrs

posted by a1234573

5 comments posted 15yrs posted by a1234573