Field-Programmable Gate Arrays

Very Slow Circuits (Was: Fast Circuits)

>> How about 1uHz? (or 1nHz or 1pHz?) >> ... >> For 1uHz, R=1Mohm, C=1F.  That isn't easy, even with an external >> cap...

1 comments posted 15yrs

posted by usenet

1 comments posted 15yrs posted by usenet

Modelsim script to print simulation progress and a TCL question

A long time ago there was a thread on comp.arch.fpga regarding how to regularly print out some information about the si...

1 comments posted 15yrs

posted by ehliar-nospam

1 comments posted 15yrs posted by ehliar-nospam

Enterpoint Recruiting

It's been a while since I have said this in public but we are recruiting again for our UK office. Details on http://www...

0 comments posted 15yrs

posted by g1

0 comments posted 15yrs posted by g1

FPGA not getting programmed

Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained to...

16 comments posted 15yrs

posted by a1234573

16 comments posted 15yrs posted by a1234573

ASM vs. RAM

Hi! Can anyone prompt me what is potential benefit of using of auto-sequencing memory (ASM) instead of standard static...

5 comments posted 15yrs

posted by purto

5 comments posted 15yrs posted by purto

FSL Problem:Data Return and Use

Hi! I wrote a custom IP peripheral in verilog and interfaced it to MicroBlaze, using Harware>Co-processor option. I can...

7 comments posted 15yrs

posted by aibk01

7 comments posted 15yrs posted by aibk01

Looking for a FPGA board

I'm looking for a FPGA OEM module for analog signal processing which contains the following: - medium size spartan 3 or...

16 comments posted 15yrs

posted by theller

16 comments posted 15yrs posted by theller

FPGA input pin connection to receive MIPI CSI-2

Hi. I'm just beginner in making fpga and i want to make MIPI CSI-2 to parallel converter in fpga. i think there are str...

1 comments posted 15yrs

posted by aisitei

1 comments posted 15yrs posted by aisitei

XC6SLX150 Coprocessor Modules

Two new FPGA coprocessor modules released today. The initial availability will be modules based on a Xilinx Spartan-6 X...

2 comments posted 15yrs

posted by g1

2 comments posted 15yrs posted by g1

Synthesizable heap-sorter for FPGA - BSD licensed sources

Hi, I have prepared a heap-sorter implementation for FPGA. The sources are licensed under the BSD license and are avail...

6 comments posted 15yrs

posted by wzab01

6 comments posted 15yrs posted by wzab01

[ANN] HercuLeS high-level synthesis tool

Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis...

6 comments posted 15yrs

posted by nikolaos.kavvadias

6 comments posted 15yrs posted by nikolaos.kavvadias

about quality of SAP training videos

Hi All, Has anyone bought SAP training videos on this site www.sapjuice.com. I would like to know the quality of their...

1 comments posted 15yrs

posted by mailtouch2

1 comments posted 15yrs posted by mailtouch2

VHDL rollover of counter

Hello, all, I am trying to make a counter follow the value of a value sent from another device. The value coming in is...

6 comments posted 15yrs

posted by elson

6 comments posted 15yrs posted by elson

job offer fpga designer genova

we are looking for an fpga designer in Genova with the following knowledges: Operating systems Windows, Linux Programmi...

0 comments posted 15yrs

posted by rosaria.quadarella

0 comments posted 15yrs posted by rosaria.quadarella

Spartan3DSP TphDCM spec question

1) Why the spec calls out negative number for input holding time ? eg. TphDCM = - 0.26 ns 2) What does that means when...

9 comments posted 15yrs

posted by ccon67

9 comments posted 15yrs posted by ccon67