I'm hoping to get some help/advise on how to design this interface. We're targeting Spartan-6.
There=92s a bidirectional, source synchronous, DDR, single-ended bus running at only 25Mhz. The problem I=92m stuck on has to do with a non- continuous clock, only running when there=92s data. For the receive side I was thinking the clock would go through a BUFIO2 and clock the data into an IDDR2. Simple enough. Then, to move that data from the IDDR2 into the core=92s clock domain I was planning to use a shallow FIFO. The problem is with the last word and clock edge (after a burst). The last clock edge only gets the data into the IDDR2 register but there=92s not another edge to complete the transfer from the IDDR2 to the FIFO.
Thanks in advance.