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Speed attained by virtex 6

Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operands, (113 bits), in Galois field inverse theory. The problem I face is that I got such results : Timing Summary:

--------------- Speed Grade: -1 Minimum period: 1.430ns (Maximum Frequency: 699.301MHz) Minimum input arrival time before clock: 0.910ns Maximum output required time after clock: 0.789ns Maximum combinational path delay: No path found =========================================================================

Process "Synthesize - XST" completed successfully

When i sent my paper to one of the journals, one of the reviewers said that it is not possible that the virtex 6 goes beyond the 600Mhz. He said try the place and route, but even though, I am getting the same frequency...

Is is true that this frequency is a fake one or perhaps an error from the synthetize tool.

Best Regards

Reply to
Fpga.Dev69
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These numbers (from the synthesis report) are estimates. Your only true timing numbers come after place and route. You'll find them in the post place & route static timing report. To get a meaningful timing report, you should add timing constraints to the design so that the tools have a target to try to achieve. With no constraints, the tools will make some attempt at optimizing the speed, but perhaps not give you the best possible results.

-- Gabor

Reply to
Gabor

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It is definitely possible to go beyond 600MHz in a virtex-6. (People where going to 250MHz in XC3195 14 years ago:

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However, for a state machine involving 113 bit operands described in a high leve approach I seriously doubt your values..

Follow the advice of the other poster: Use post place and rout timing and provide timing constraints for your clock signals to get a better timing report.

Regards,

Kolja

Reply to
Kolja Sulimma

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