Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

CPU Design in Xilinx Spartan 3E

Hello Every body, I have written a code in VHDL for 8 bit simple cpu and also have the test bench for this. The Opcodes...
8 comments posted 14yrs
posted by tu_ind
8 comments posted 14yrs posted by tu_ind

Synchronizing Virtex-6 RocketIOs on RX path

Hi in a project I am using a Virtex-6 with GTX RocketIO transceivers which I want to interface with a 4x 6.5 Gb/s inter...
2 comments posted 14yrs
posted by berti.schueler
2 comments posted 14yrs posted by berti.schueler

FPGA Area

Hi all, I have question on measuring FPGA area. Measuring area cost of the FPGA implementation is tricky because there...
6 comments posted 14yrs
posted by shakith.fernando
6 comments posted 14yrs posted by shakith.fernando

Error JTAG chain problem detected

My design worked for about 3 hours and now gives me this error. I just can't understand what is wrong with it now. I di...
2 comments posted 14yrs
posted by imajstorovic
2 comments posted 14yrs posted by imajstorovic

configuring an Altera Cyclone 3

Hi, I have an FPGA design that works from JTAG, and now I want to burn a serial flash chip so it will configure itself...
7 comments posted 14yrs
posted by jlarkin
7 comments posted 14yrs posted by jlarkin

Migrating Spartan2 design (xnf)

Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate thei...
4 comments posted 14yrs
posted by nico
4 comments posted 14yrs posted by nico

JTAG to obsolete Lattice MACH131?

I've got a strange one. Someone's asked me to reprogram an old MACH131SP device, dating from about '95-98. Are any of y...
2 comments posted 14yrs
posted by nospam
2 comments posted 14yrs posted by nospam

Touchscreen For Terasic Technologies DE0 Nano

Hi, I am looking for a touchscreen for an DE0 Nano. Terasic's LTM touchscreen is supposed to work but the LTM manual do...
1 comments posted 14yrs
posted by snowybrown
1 comments posted 14yrs posted by snowybrown

Strassen algorithm in vhdl

hi all I am currently struggling trying to write Strassens Algorithm for matrix multiplication in VHDL. I have written...
2 comments posted 14yrs
posted by rsr1991
2 comments posted 14yrs posted by rsr1991

Using both Verilog and VHDL for Xilinx simulation

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for inst...
1 comments posted 14yrs
posted by michael_laajanen
1 comments posted 14yrs posted by michael_laajanen