Synchronizing Virtex-6 RocketIOs on RX path

Hi

in a project I am using a Virtex-6 with GTX RocketIO transceivers which I want to interface with a 4x 6.5 Gb/s interface on the RX side. One project contraint is not to use any channel coding, i.e. only 8B data. So I have 4x

6.5Gb/s that I have to synchronize on the RX path. That gives me two major challanges:

a) Somehow achieve a clock recovery b) Synchronize the incoming data

Due to the fact that I am not allowed to use a specific channel coding, I cannot get the clock signal extracted from my data. So my idea is to use one additional channel to send a 1-0-pattern to get a clock reference for the whole interface. Use this as RXRECCLK (RX recovered clock) to clock the other RocketIOs. Is this possible? If so, done! Then use a training pattern on the other channels to be able to shift and deskew the data (given that the skew does not change over time). Thereafter transmit the data over the 4 parallel channels.

So what do you think of this concept? Is it feasible? Any other suggestions?

Thanks, Berti

Reply to
Berti Schueler
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Your solution sounds remarkably like Channel-Link, and it's not likely to work at 6.5 Gbps. The problem (even if it were possible to wire the bit clocks together inside the V6) is that you're looking at a daunting task to match the prop delays between data and clock channels. You have a much better chance of success using 8B-10B encoding and increasing the clock rate to allow the required throughput. Is the Rx side also implemented in V6?

-- Gabor

Reply to
Gabor

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I may have a similar problem so just brainstorming here: is it possible to use the recovered clock from the clock channel channel to a PLL to have better clock performance?

Reply to
Verictor

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