Because the Xilinx Spartan2 is going to be discontinued in the near future one of my customers asked me to migrate their designs to a newer Xilinx FPGA. Perhaps Spartan 6 or Artix 7. The problems are:
- these designs where originally created for the 4000 series using schematic capture (XNF format) then moved to Virtex and finally to Spartan 2. Newer parts where written in VHDL though.
- The designs contain some async logic (especially the part talking to an MCU using an addres/data bus) and locally divided clocks.
- I'm worried at some point extra gates where added to increase the delay. This will break in a much faster FPGA.
- The design contains bi-directional busses in several places.
My approach would be to convert the XNF parts to VHDL (does someone sell software to do that?) and then check for anomalies due to changes in the FPGA architecture. This could be a huge task. The XNF parts represent several years worth of work.
Any suggestions on how to tackle such a project?