Virtex 6 System Monitor sensor readings in ChipScope gives weird values

Hi =20 We are doing initial testing of a new Virtex-6 based board that we develope= d. We are having problems when trying to access the system monitor informat= ion over JTAG. It is constantly showing a die temperature of -29 degrees, a= nd incorrect voltages for VCCINT, VCCAUX and the VREFP pin on the System Mo= nitor itself. We've verified that the correct voltages are present on all i= nputs on the BGA. =20 We've successfully configured the device over the JTAG chain, thus we don't= think the problem is over there. We get the wrong values before and after = configuration (they stay constant all the time). =20 I've checked the way the connections to the device have been done many time= s, and can't find anything wrong with it. I also asked this question on the= Xilinx community forums and I've uploaded the relevant part of the schemat= ics over there:

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=20 Any ideas on where to look next for things that can go wrong will be much a= ppreciated. =20 Thanks, Jaco

Reply to
Jaco Naude
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Your solution is posted over at the Xilinx forum:

The VREFP is connected to 2.5V, the same as AVDD. However, the reference voltage is 1.25V for V6 (and 7series).

If you do not have access to a 1.25V reference on the PCB, you can tie VREFP to AVSS, and an internal reference will be used.

The accuracy of measured values when using the internal reference is less accurate. I believe this is ~1% error. The user guide and data-sheet will have the accuracy numbers for both internal and external reference modes.

We are having problems when trying to access the system monitor information over JTAG. It is constantly showing a die temperature of -29 degrees, and incorrect voltages for VCCINT, VCCAUX and the VREFP pin on the System Monitor itself. We've verified that the correct voltages are present on all inputs on the BGA.

think the problem is over there. We get the wrong values before and after configuration (they stay constant all the time).

and can't find anything wrong with it. I also asked this question on the Xilinx community forums and I've uploaded the relevant part of the schematics over there:

formatting link

appreciated.

Reply to
razzy

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