Field-Programmable Gate Arrays

Major New Release of Public-Domain FPGA Architecture and CAD Research Software: VTR 1.0

For those interested in FPGA CAD and architecture research, we are pleased to announce the full release of the Verilog-...

0 comments posted 14yrs

posted by jonathanscottrose

0 comments posted 14yrs posted by jonathanscottrose

problem with Global Clock pin and normal IO pin as Clock input

hi i am trying to detect falling edge of a 200ns pulse(WriteStrobe) synchronously with this code. GlobalClk is 100MHz(1...

5 comments posted 14yrs

posted by nba_baheri

5 comments posted 14yrs posted by nba_baheri

JAM Stapl player on 64 bit platform?

Hi, A few years ago I've prepared the customized version of JAM STAPL Player, well suited for operation in VME based en...

2 comments posted 14yrs

posted by wzab01

2 comments posted 14yrs posted by wzab01

Anybody here got a Xilinx ML605?

I'm having trouble running the application described in XAPP740 (Designing high-performance video systems with the AXI...

4 comments posted 14yrs

posted by pete_fraser

4 comments posted 14yrs posted by pete_fraser

LUT6 FPGAs and Carry Logic

Hallo. Some questions about Xilinx LUT6 FPGAs (my WebPack Toolchain is a little outdated, and the newer LUT6-FPGAs don'...

15 comments posted 14yrs

posted by jansaccount

15 comments posted 14yrs posted by jansaccount

MPMC simulation

Hi, I am simulating MPMC with Isim version 12.4. I have written a test bench to give inputs to microblaze instance. Her...

0 comments posted 14yrs

posted by saylee.24

0 comments posted 14yrs posted by saylee.24

Dangling all pins, DIA0 through DIA31

I'm creating a dual-port ROM, both sides are the same: 7-bit address, 32-bit data. Very simple ISE 13.3 project can be...

6 comments posted 14yrs

posted by aleksazr

6 comments posted 14yrs posted by aleksazr

Life after XDL

Regards,

2 comments posted 14yrs

posted by neil.steiner

2 comments posted 14yrs posted by neil.steiner

Problem with post-route simulation

The whole ISE project (VHDL) can be found here: http://www.mediafire.com/?wvvvcjrjl67lcnr Besides ISE project, it also...

3 comments posted 14yrs

posted by aleksazr

3 comments posted 14yrs posted by aleksazr

'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation

I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2;...

3 comments posted 14yrs

posted by heavenfish

3 comments posted 14yrs posted by heavenfish

Free GUI top level integration tool for Verilog and VHDL

VTC has been developed for very long time. It has been used in many projects and proven to be useful. It should have be...

3 comments posted 14yrs

posted by vtxsupport

3 comments posted 14yrs posted by vtxsupport

Re: A smallish starter Kit for led control

> We have a range of solutions but a lot depends on what sort of drive > you want and how that is going to be implement...

0 comments posted 14yrs

posted by sala.nimi

0 comments posted 14yrs posted by sala.nimi

Xilinx Artix-7 availability

did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7...

4 comments posted 14yrs

posted by arne

4 comments posted 14yrs posted by arne

Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems

I have an 8X PCIe core in a Virtex6HXT (version 2.5, the latest in 13.4). It's configured for Gen2 but it's coming up G...

0 comments posted 14yrs

posted by schvantzkoph

0 comments posted 14yrs posted by schvantzkoph

Difference between Xilinx isim and modelsim

Is it allowed to pass a member of a std_logic_vector to the rising_edge function? When doing this, isim doen's detect a...

6 comments posted 14yrs

posted by guenter.wolpert

6 comments posted 14yrs posted by guenter.wolpert