Latest threads in Field-Programmable Gate Arrays

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea

The Embedded System on Chip Lab of the Hallym University seeks to recruit promising PhD and MSc research students. The...

0 14yrs

jeonggun.lee

0 14yrs jeonggun.lee

Using both Verilog and VHDL for Xilinx simulation

Hi, How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA? I need for inst...

1 14yrs

michael_laajanen

1 14yrs michael_laajanen

Major New Release of Public-Domain FPGA Architecture and CAD Research Software: VTR 1.0

For those interested in FPGA CAD and architecture research, we are pleased to announce the full release of the Verilog-...

0 14yrs

jonathanscottrose

0 14yrs jonathanscottrose

problem with Global Clock pin and normal IO pin as Clock input

hi i am trying to detect falling edge of a 200ns pulse(WriteStrobe) synchronously with this code. GlobalClk is 100MHz(1...

5 14yrs

nba_baheri

5 14yrs nba_baheri

JAM Stapl player on 64 bit platform?

Hi, A few years ago I've prepared the customized version of JAM STAPL Player, well suited for operation in VME based en...

2 14yrs

wzab01

2 14yrs wzab01

Anybody here got a Xilinx ML605?

I'm having trouble running the application described in XAPP740 (Designing high-performance video systems with the AXI...

4 14yrs

pete_fraser

4 14yrs pete_fraser

LUT6 FPGAs and Carry Logic

Hallo. Some questions about Xilinx LUT6 FPGAs (my WebPack Toolchain is a little outdated, and the newer LUT6-FPGAs don'...

15 14yrs

jansaccount

15 14yrs jansaccount

MPMC simulation

Hi, I am simulating MPMC with Isim version 12.4. I have written a test bench to give inputs to microblaze instance. Her...

0 14yrs

saylee.24

0 14yrs saylee.24

Dangling all pins, DIA0 through DIA31

I'm creating a dual-port ROM, both sides are the same: 7-bit address, 32-bit data. Very simple ISE 13.3 project can be...

6 14yrs

aleksazr

6 14yrs aleksazr

Life after XDL

Regards,

2 14yrs

neil.steiner

2 14yrs neil.steiner

Problem with post-route simulation

The whole ISE project (VHDL) can be found here: http://www.mediafire.com/?wvvvcjrjl67lcnr Besides ISE project, it also...

3 14yrs

aleksazr

3 14yrs aleksazr

'x' state on one bit of the input bus of an adder cause the output bus be all 'x' during simulation

I have an adder: module adder( input [1:0] add1, input [1:0] add2, output [2:0] addout ); assign addout = add1 + add2;...

3 14yrs

heavenfish

3 14yrs heavenfish

Free GUI top level integration tool for Verilog and VHDL

VTC has been developed for very long time. It has been used in many projects and proven to be useful. It should have be...

3 14yrs

vtxsupport

3 14yrs vtxsupport

Re: A smallish starter Kit for led control

> We have a range of solutions but a lot depends on what sort of drive > you want and how that is going to be implement...

0 14yrs

sala.nimi

0 14yrs sala.nimi

Xilinx Artix-7 availability

did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I am interested in the XC7...

4 14yrs

arne

4 14yrs arne

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