Field-Programmable Gate Arrays

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recomendation on a processor core

hi, after few years i want to restart FPGA development once again - initially f= or personel fun, but later may move in...
7 comments posted 14yrs
posted by manusha1980
7 comments posted 14yrs posted by manusha1980

XSpi_Transfer within interrupt context

I'm using the standalone bsp for a ppc440 on a Virtex 5. I have a scenario where I have to read from an external chip o...
1 comments posted 14yrs
posted by baringforge
1 comments posted 14yrs posted by baringforge

The Xilinx Definition Language

Does anybody somewhere have a backup of this document, xdl.html, which was part of ISE 6.3? Regards, Jurgen
2 comments posted 14yrs
posted by jurgen.defurne
2 comments posted 14yrs posted by jurgen.defurne

strange letter from Xilinx

In 2001 I bought a seat of Xilinx Foundation (before Ise). I did not renew the service contract because it was working...
4 comments posted 14yrs
posted by jmelson
4 comments posted 14yrs posted by jmelson

Partial reconfiguration: bus macros

Hello, I am trying to do DPR on an Atlys board, which uses Spartan-6. It seems I c= an only solve my problem if I rever...
0 comments posted 14yrs
posted by jurgen.defurne
0 comments posted 14yrs posted by jurgen.defurne

Data Transfer from PC to FPGA through USB

Hallo guys, I'm pretty new to hardware programming. I'm currently working on a project and I have to create a communica...
7 comments posted 14yrs
posted by mtnyenty
7 comments posted 14yrs posted by mtnyenty

FPGAs directly plugged into CPU socket

I'm looking to purchase an FPGA that plugs directly into motherboard CPU sockets. I've only been able to find this DRC...
0 comments posted 14yrs
posted by jsjones721
0 comments posted 14yrs posted by jsjones721

RPMs in xilinx 13.2

Hi, I am using xilinx 13.2 for synthesis and implementation of my design. I wanted to create RPMs of some small logic s...
3 comments posted 14yrs
posted by a1234573
3 comments posted 14yrs posted by a1234573

Best FPGA for algorithmic acceleration

Hello, I'm looking at different options to use FPGAs as coprocessors for algorithmic acceleration. Between the Xilinx V...
9 comments posted 14yrs
posted by jfix71
9 comments posted 14yrs posted by jfix71

Watchdog reset for fpga designs

hi i 'm designing a board with fpga spartan 3(Industrial series) . while testing the board, specially when there is spi...
4 comments posted 14yrs
posted by nba_baheri
4 comments posted 14yrs posted by nba_baheri

Any people having experience with HWICAP?

Dear all, As a lab project I need to check the possibilities of the HWICAP interface in the context of setting up a SoC...
2 comments posted 14yrs
posted by jurgen.defurne
2 comments posted 14yrs posted by jurgen.defurne

LX9 and internal reset - Do I need one?

Hi, I am slowly implementing my morse keyer using a Avnet LX9 board. BTW, thanks all for your sugggestions, in the end...
3 comments posted 14yrs
posted by giuseppe.marullonospam
3 comments posted 14yrs posted by giuseppe.marullonospam

Very poor Xilinx experience

I'm hoping someone at Xilinx reads this, because I can't find any other way to get through to anyone to help me. Short...
10 comments posted 14yrs
posted by google
10 comments posted 14yrs posted by google