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Watchdog reset for fpga designs

hi i 'm designing a board with fpga spartan 3(Industrial series) . while testing the board, specially when there is spike on any input pin of fpga, fpga enters unknown sate and won't do its job correctly, but after reset it continues working. is it a common design practice to have an external watchdog timer to reset the fpga in fpga based boards in case it is in unknown state, like watchdog timer in microcontrollers? I thought that fpgas are more stable than microcontroller in response to noise, but in my test design I experienced the same thing similar to microcontrollers.

are gates in fpga altered due to noise?? tnx in advanced for any comment

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Reply to
nba83
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Never known an FPGA (Altera) to crash in over 25 years. Maybe your PSU volts are suspect. I always enable the FPGA CRC checking which will cause the device to 'reboot' from external memory if the internally calculated CRC ever differs from the CRC supplied during loading. Maybe Xilinx do not have this feature?

Andy

Reply to
Andy Bartlett

Define "spike" -- do you mean a runt pulse, or do you mean an overvoltage spike?

The FPGA designers that I work with personally are sensitive to their designs locking up or otherwise getting wedged in illegal states, and have a plethora of design measures to prevent that from happening.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Reply to
Tim Wescott

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it

y

By "reset" do you mean a re-programming/configuration of the FPGA, or a res= et of the already configured logic?

I'm guessing that you mean the latter, and that the internal logice (a stat= e machine, perhaps) is getting into an illegal state. Further guessing tha= t a short pulse/spike is being seen by some FFs, but not all of those to wh= ich it fans out to. I.E. metastability through lack of proper synchronisat= ion of the incoming signal.

As Tim says ther are a number of techniques used to avoid these kinds of pr= oblems, depending on the nature of the logic and the degree of resilience r= equired. A first line of defence is to register all inputs with the FFs cl= ocked by the same clock as used by the logic that it feeds, better still is= two cascaded FFs.

Careful design of the state machines themselves is also important, e.g. tra= pping illegal states and transitioning to a legal one (usually the reset or= initial state).

Without the specifics of your case it is difficult to give a more specific = solution, but I hope that we have pointed you in the right direction.

--=20 Andy McC

Reply to
andy.mcclelland

How large is your spike. If it exceeds something like 4.6V then you are exceeding the specification of the device and all sorts of strange things might happen. Which variety of Spartan-3 do you have 3, 3E or

3A?

Also look at the state machine reasoning mentioned elsewhere in the post responses. Spartan-3 flip-flops etc. can respond to very narrow glitches and you cannot rely on those being ignored by the device. In this sphere some flip-flops might respond to a spike and others not so state machines can go into funny illegal states and so on.

John Adair Enterpo> hi

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it

y
Reply to
John Adair

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