Any people having experience with HWICAP?

Dear all,

As a lab project I need to check the possibilities of the HWICAP interface in the context of setting up a SoC using MicroBlaze and doing a partial reconfigure (in this case most probably through the serial interface). I am doing this on an Atlys board.

I have a working SoC and the example C code runs, with affirmative exit status on the HWICAP.

When I embed the SoC in a top level VHDL for ISE, everything runs still OK.

However, when I add a small logic block, connected to the switches and LED's of the board, the HWICAP does not initialize anymore. The rest of the circuit does work, because I am able to run the program. Adding more diagnostic code showed that the HWICAP fails to initialize. When I disconnect the logic block, everything runs fine again.

I wrote a bitstream decoder, and inspecting all the generated bitstreams showed that the PERSIST is always off, so the problem is not there either.

I have a topic on the Xilinx forums, I get referenced to the 'free SEU Monitor IP core for S6' but when I search for it, I only get references to that topic on the forum or the Xilinx SEM IP.

The next thing I will try is to create the two designs, with and without logic block, and see if I can create a differential bitstream and use that to load through the working HWICAP design.

Any other ideas and tips are welcome.



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So, this way of working fails because of the following:

ERROR:Bitgen:339 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, is not compatible with partial bitstreams. For more information, please reference Xilinx Answer Record 39999. Error:Bitgen:157 - Bitgen will terminate because of the above errors.

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I did overcome one obstacle. By doing post-synthesis floorplan design and c= onstraining my logic block onto another part of the FPGA, I succeeded into = getting what I wanted: a working SoC, a working separate logic block, and H= WICAP which works again. So, somewhere there must have been some interferen= ce between this logic block and HWICAP circuitry.

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