1. Home
  2. Field-Programmable Gate Arrays
  3. LX9 and internal reset - Do I need one?

LX9 and internal reset - Do I need one?

Hi, I am slowly implementing my morse keyer using a Avnet LX9 board. BTW, thanks all for your sugggestions, in the end I decided for this one (Gabor, you won!).

I stuffed a lot of things in the project (A serial LCD, several PMODs, like an encoder, a BF ampli and so on), I plan to add USB Host functionality to save settings on a USB stick (HobbyTronics has some

*nice* gadgets!):

formatting link

To cut a long story short, I think I will run out of pins (16 in total!).

I would like to know if I could save one pin for the reset.

I actually have a active high pushbutton called user reset, and used that to reset the board when I need it. This one is not one of the 16 user I/O I have.

I don't think it will do the reset trick on power up, so I guess everything will start inizialized to zero.

My default state on each FSM is 0, so no big deal.

I use that signal as reset, and so far everything is fine. I use positive logic for reset, and the momentary switch is active high.

Now, is it enough or should I need a dedicated reset pin that runs high at startup to be sure?

In the testbench obviously I simulate the pressing of the button, but in a real case scenario, how would it behave if I would use one hot encoded FSM for example (no default 0 state then)?

TIA.

Giuseppe Marullo

Reply to
Giuseppe Marullo
Loading thread data ...

- I suggest you to built in the FPGA a so called "Power On Reset" circuit, followed by some "Reset Bridge" (one for each clock domain).

- As you certainly already know, when using an (internal) power on reset, the external reset pin can be optional.

Claude

--- Posted via news://freenews.netfront.net/ - Complaints to snipped-for-privacy@netfront.net

Reply to
Claude Sylvain

Claude, many thanks about your answer.

This is what I wrote to implement the automagic reset time:

reg [3:0] rst_buffer;

wire user_reset = ~rst_buffer[3]; // I need a active reset signal

always @(posedge user_clock or posedge user_button)

if (user_button == 1'b1) // the pushbutton is high when pressed rst_buffer - As you certainly already know, when using an (internal) power on > reset, the external reset pin can be optional.

I am still learning things, this is for hobby. I have the pushbuton already on the board, so ti does make sense to avoid using another pin just for this.

Giuseppe Marullo

Reply to
Giuseppe Marullo

If you never need to reset the FPGA after configuration, then you don't need a reset pin. Configuration itself provides a complete initialization of all internal registers. However, it is a good idea to delay the startup of state machines after configuration because the skew of the global reset net is large, and the startup clock probably isn't synchronous to your design. So usually I do essentially what you did but without the button:

reg [3:0] rst_buffer = 4'b1111; // Active high reset wire user_reset = rst_buffer[3]; // still active high always @ (posedge clk) rst_buffer

Reply to
Gabor

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.