Field-Programmable Gate Arrays

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Re: Ball-park price of Xilinx Virtex 7 FPGA?

> I understand that the price depends on the volume etc > but I would like to know the per unit price of Virtex 7 FPGA....
17 comments posted 14yrs
posted by bon
17 comments posted 14yrs posted by bon

Low latency FPGA options

Hello, I am looking to use FPGA's as specialized coprocessors to increase performance on different applications. I woul...
3 comments posted 14yrs
posted by jfix71
3 comments posted 14yrs posted by jfix71

Could you explain these speed spec to me?

Hi, I get the following data from a on-line slide on MAP decoder. I think "Speed" is about the max clock rate. How abou...
1 comments posted 14yrs
posted by rxjwg98
1 comments posted 14yrs posted by rxjwg98

FPGA communication with a PC (Windows)

Hello all, My team needs to design our own piece of testing equipment for our project. I'll spare you the gory details,...
33 comments posted 14yrs
posted by bill.valores
33 comments posted 14yrs posted by bill.valores

FPGA + Mess o' RAM

Does anyone have any experience connecting an FPGA to a serious mess of DRAM? I'm thinking of something on the order of...
3 comments posted 14yrs
posted by rgaddi
3 comments posted 14yrs posted by rgaddi

Digital Tachometer VHDL

Hi, I have this project where I have to design a tachometer using VHDL. The thing is I m pretty new to the field of ele...
6 comments posted 14yrs
posted by bine.bai
6 comments posted 14yrs posted by bine.bai

Why are my S3A pins getting destroyed?

I have a S350A VQFP100 on my custom board, with all the pins connected to large pads all around the chip. I have destro...
2 comments posted 14yrs
posted by aleksazr
2 comments posted 14yrs posted by aleksazr

Spartan 3A counter speed ?

Hello, Does anybody have a very rough estimate of how fast you can run a 32-bit counter in a Spartan 3AN FPGA? Thanks, J...
10 comments posted 14yrs
posted by jmelson
10 comments posted 14yrs posted by jmelson

Virtex6HXT PCIe 8X Gen2 timing closure problem

I'm having a terrible time getting the V6 PCIe core to consistently meet timing, it works occasionally but usually it m...
1 comments posted 14yrs
posted by schvantzkoph
1 comments posted 14yrs posted by schvantzkoph

Spartan 3 DiffPairs restricted to Banks 0 and 2?

On a PCI Card I got a XC3SD1800A-4FGG676C. While trying to establish a differential output pair on Pins K23,K22, i got...
2 comments posted 14yrs
posted by tobias.kahre
2 comments posted 14yrs posted by tobias.kahre

Internal BUS design: MUX or OR-GATE?

Hello, I have an internal BUS for all the registers in different modules. I found it is inconvenient to build a MUX for...
7 comments posted 14yrs
posted by heavenfish
7 comments posted 14yrs posted by heavenfish

Comparing relative power consumption

I am struggling to find a solution to my problem: I would like to get a (very) rough idea of the relative levels of pow...
0 comments posted 14yrs
posted by ajpkane
0 comments posted 14yrs posted by ajpkane

Back from Xilinx trainings

Hi: I spent the last two weeks at Xilinx in San Jose taking Doulos' "Comprehensive Verilog" and the "Essentials and Des...
0 comments posted 14yrs
posted by crobcBOGUS
0 comments posted 14yrs posted by crobcBOGUS