Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

When will outsourcing hit FPGA'ers?

My friend has been telling me that the ASIC design industry suffers from extremely expensive tooling (a single Design C...
2 comments posted 21yrs
posted by none
2 comments posted 21yrs posted by none

Altera's power consumption net seminar

Hi, I just finished viewing the fpga power consumption net seminar that Vaughn presented today. I found it informative...
5 comments posted 21yrs
posted by eternal_nan
5 comments posted 21yrs posted by eternal_nan

LVPECL, Virtex II and the EP445

I have a bank of On Semiconductor EP445 1:8 deserializer chips operating at LVPECL levels. The eight outputs are single...
13 comments posted 21yrs
posted by nospam
13 comments posted 21yrs posted by nospam

[FS]: ADS5500IPAP ADC 14BIT 125MSPS 64-HTQFP

Dear colleage engineers, I have for sale twenty-eight ADS5500IPAP (ADC 14BIT 125MSPS 64-HTQFP), of course unused, seale...
0 comments posted 21yrs
posted by microelectro
0 comments posted 21yrs posted by microelectro

Problem with flip-flops on Spartan 3

So my simulations aren't coming out right. I've got a big block of VHDL that synthesizes down to a decent size block of...
3 comments posted 21yrs
posted by rgaddi
3 comments posted 21yrs posted by rgaddi

using the for-loop !

Hi .. why cant i synthesize a module where i have a for-loop which runs thourgh a signal std_logic_vector data_in .......
0 comments posted 21yrs
posted by hansonj
0 comments posted 21yrs posted by hansonj

DDR SDRAM interface working with AMBA-AHB

Hi folks, I'm trying to get a DDR-SDRAM controller work as an AHB slave. According to the transfer timings in the AMBA...
1 comments posted 21yrs
posted by kevinzh
1 comments posted 21yrs posted by kevinzh

CLOCK__SIGNAL constraint! pls help

Hi, I'm doing my final uni project in VHDL using the xilinx spartan 2 pegasus FPGA board but have hit a small snag. Whe...
0 comments posted 21yrs
posted by alistairlamb
0 comments posted 21yrs posted by alistairlamb

Programming with XC17S15

Hi, does anyone know the difference between a Motorola S-record and the Motorola EXORmacs format, if there is any? Thank...
0 comments posted 21yrs
posted by anton.bachmeier
0 comments posted 21yrs posted by anton.bachmeier

OT: EDA tools

We've been using Altium's P-CAD for a few years (started as TangoEDA). Currently running 2002 and very unlikely to upgr...
3 comments posted 21yrs
posted by 0_0_0_0_
3 comments posted 21yrs posted by 0_0_0_0_

Xilkernel: configure to use 2 PPCs

Is xilkernel configurable to use 2 PPCs in a Virtex II? It seems that all the Xilinx literature I have found has xilker...
4 comments posted 21yrs
posted by joeylrios
4 comments posted 21yrs posted by joeylrios

ISE 7.1 on Fedora Core 3

There is a simple work around for the libcurl problem with the 7.1 installer, just link the newer libcurl library to li...
5 comments posted 21yrs
posted by bjrosen
5 comments posted 21yrs posted by bjrosen

nallatech BallySHARC boot JTAG problem

I'm working with Nallatech BallySHARC module and I have a problem to boot DSP through JTAG cable because it's done corr...
0 comments posted 21yrs
posted by dario.gall
0 comments posted 21yrs posted by dario.gall

Chipscope and Virtex4 LX25 ES

Hi, Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES parts and the JTAG chains, with workarounds for...
1 comments posted 21yrs
posted by jwilliams
1 comments posted 21yrs posted by jwilliams