My friend has been telling me that the ASIC design industry suffers from extremely expensive tooling (a single Design Compiler license is over $100k USD), ridiculously high NRE (mask-set for any standard-cell fab process), and equally expensive/difficult "back-end" (place&route) workflow.
On the opposite end, I eye with envy the FPGA designer's world with very low startup costs. A hobbyist can buy a simple (