Altera's power consumption net seminar

Hi,

I just finished viewing the fpga power consumption net seminar that Vaughn presented today. I found it informative and, to me, it apeared to be objective.

According to Vaughn's experiments and measurements, Stratix 2 exhibits lower dynamic power dissipation in the core and similar power dissipation in the IO; beyond that his experimental results contend that the highly touted static/leakage power advantage that V4 is supposed to have is very minor; some might even say negligable.

I am very curious to read Austin and Peter's opinions of this presentation.

Ljubisa Bajic ATI Technologies

---------- My opinions do not represent those of my employer.

Reply to
Ljubisa Bajic
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exhibits

These guys are all biased. When you look at details, they show their side of the story. Power ? Big deal ! There are other more pressing issues ! High end FPGAs hardly go in portable devices ! ;-)

Reply to
che_fong

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Che Fing and Ljubisa.

I wanted to comment on the static/leakage power advantage of V4 vs Stratix II, which is claimed to not exist based on Vaughn's experiments. I have personally measured Static Power in both Virtex-4 LX60, LX100, 2S60, and 2S90. Virtex-4 has 3-4x lower Static Power.

1) He did not make quote experimental results as yielding almost identical static power for Virtex-4 and Stratix II. If you look carefully at all actual bench measurements of total power for various designs, which were presented. They have total power (at 25 C). They all show a significant advantage for Virtex-4 (look at the DC i.e. zero frequency data points in the slides).

2) Vaughn's method for calculating Virtex-4 and Stratix II worst case power was as follows: a) For Altera's Stratix II he did the following: i) Use Power Play 2.1 and Select a Part and then select worst case. ii) Set the ambient temperature in such a way that it results in an 85 C junction temperature, including rise of junction due to ThetaJA iii) Record the sum of Vccint Power and VccPD power as Static Power. b) For Xilinx he did the following: i) Use Xilinx Web Power 4.1 and Select a Part. Xilinx doesn't report worst case static power as part of its tool, but does report Static Power versus junction temperature, similar to the PowerPlay 2.1 tool ii) Vaughn say he then uses a 2.5x worst case to typical ratio for Static Power that has been publicly touted by Xilinx as a guideline to customers. iii) He then sums the Vccint Power and the VccAux power. He then multiplies the sum by 2.5x.

The conclusion is that Virtex-4 and Stratix II have similar Static Power and further that Vccaux power in Virtex-4 is 21-40% of total Static Power when we consider, when we consider worst case.

Here's the error. Xilinx doesn't have a multiplier on Vccaux power of 2.5 (we have never stated this publically or privately). We have stated a 2.5x multiplier ONLY on Vccint power for typical to worse case. There is no scaler applied to Vccaux power, because the number is the Xilinx tools is in fact quite invariable over process. Even the 2.5x value on Vccint only is very conservative.

This error in using the 2.5x multiplier on Vccaux results in the Xilinx Virtex-4 having the originally stated huge advantage in Static Power compared to Stratix-II, both in typical and worst case.

Matt

che_f> Ljubisa Bajic wrote:

Reply to
Matt Klein

Well if you have a " Power ? Big deal ! " attitude, it's gonna be difficult for you to design a portable device with a high-end FPGA. Those of us who know that power _is_ a big deal seem well enough able to do it though. Cheers, Syms.

Reply to
Symon

Power is important even in non-portable applications. In telecomm applications, which are a major market for fpga's, heat dissipation is a very real problem and determins to some extent how densely racks can be stacked with linecards or similar electronics. Not to mention that no-one likes their power bills to be larger than neccessary.

Ljubisa Bajic ATI Technologies

--- My opinions do not represent those of my employer

Reply to
Ljubisa Bajic

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Matt Kle> 1) He did not make quote experimental results as yielding almost =

identical

all

were

significant

in

We measured static power, and it is in line with the typical values = predicted by the power estimators, so both the Stratix II and Virtex4 = devices measured were reasonably typical. The 25 C ambient temperature, = typical silicon results for static power show a small static power = advantage for Virtex4. The advantage is about 40 mW for the LX25 vs. = the 2S15, and about 180 mW for the LX25 vs. the 2S30.

The more important comparison is the worst-case silicon, 85 C junction = temperature total power comparison. For that comparison, we have to = rely on the power estimators of Xilinx & Altera, since we can't buy tens = of thousands of Xilinx units across multiple wafers and lots to create a = worst-case silicon model. That comparison again shows a small static = power advantage for Virtex4: from 0 W to 690 mW, depending on the = device you're comparing.

See

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to = view the whole NetSeminar on archive. =20

2.5
2.5x

no

is

That does not match what we're seeing in the customer base. We're often = visiting the same customers as Xilinx, and we see customers being = advised to multiply Vccint by 2.5X (matching your comment above), but we = also see Xilinx advising Vccaux worst-case leakage is 2X to 2.5X = (depends on which customer you ask) typical.

In any case, the worst-case silicon, 85 C static power comparison is not = affected dramatically by which multiplier we use for Vccaux, and the = total power comparison (static + dynamic + IO) is of course affected = even less. The table below summarizes the power consumption for the =

2S180 vs. the LX200 for 3 different Vccaux typical to worst-case = multiplier assumptions.

Comparisons below: worst-case silicon, junction Temp =3D 85 C, typical = utilization 200 MHz design, equivalent Virtex4 & Stratix II utilization = (see NetSeminar for details) =20 Static Dynamic + IO Total Power

2S180 5.46 W 8.5 W 14 W LX200 (Vccaux =3D 2.5X typical) 5 W 11.3 W 16.3 W LX200 (Vccaux =3D 2X typical) 4.79 W 11.3 W 16.1 W LX200 (Vccaux =3D typical) 4.38 W 11.3 W 15.7 W

So you can see, the overall power comparison doesn't move much, and even = the static power comparison only moves moderately, no matter what Vccaux = multiplier is used. =20

Xilinx

I addressed this question in the NetSeminar. There are two problems = with the Xilinx white paper that makes this claim.

  1. It neglects to add Vccaux static power to the Virtex4 static power, = but a significant part (for typical silicon 21% to 40%, depending on the = device density) of the Virtex4 static power comes from Vccaux. =20
  2. It compares one Stratix II device to one Virtex4 device. However, = process variation results in a tremendous variation in static power from = the best-case leakage device (higher than spec'd Vt, longer than Spec'd = channel) to the worst-case leakage device (lower than spec'd Vt, shorter = than spec'd channel). It is common to see worst-case to best-case = silicon vary in static power by 3X to 5X (the exact value depends on the = steps you took in design & layout to create process-variation reducing = structures, and exactly how good your process control is). Hence = comparisons on single units aren't very useful
Reply to
Vaughn Betz

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