DSP designs that exceed provided embedded arithmetic hardware

Hi Syms,

Thanks for your reply.

The general consenus as far as I am aware seems to be that designers will want to use dedicated FPGA silicon blocks that will accomplish a given task before implementing such tasks on the generic fabric.

I am just curious to see exactly how designers are using the "lego blocks" they have available to them hence I thought I would see what the inhabitants of this ng do.

Cheers,

Ken

We've some big DSP applications on VirtexIIs with 100% of multipliers or 100% of Ram blocks used (and over 90% of logic used). In VIIs, this sometimes is tricky since they share ressource, and this can put some restrictions on how the blocks (DSP+Ram) can be parameterized to coexist. You may also find difficult to partition the operators between dedicated and logic since the synthesis tool may have a global flag... Manual inference is often the solution. Globally, we've been pleasantly surprised by the routability of very dense arithmetic (DSP) designs (both in Xilinx and Altera parts btw). Last, we're not using (well almost not) ready-made IPs, so we retain control of how the operators are inferred (and which variant), so it's probably a safer situation.

Bert Cuzeau