Xilkernel: configure to use 2 PPCs

Is xilkernel configurable to use 2 PPCs in a Virtex II? It seems that all the Xilinx literature I have found has xilkernel running only one PPC. I know the xilkernel source is available, but would like to stay away from it if possible. Anyone gotten a dual-core running with xilkernel? Thanks.

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Xilkernel is not an SMP (Shared multi-processor) kernel. So, in that sense - No, it cannot run on two PPCs.

If you mean, can you run it on two different PowerPCs independently, then there is no reason why it would not work. Both the kernels would be completely independent and ignorant of the other. There are also no constructs to managed shared memory between the two processors in Xilkernel.


Joseph wrote:

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Vasanth Asokan

Thanks Vasanth,

Can you or anyone else reccomend an SMP OS for the Virtex II? Specifically, I am working on the ML310 board. There isn't much literature on running both cores at once, so any advice is appreciated. Currently I am looking at the MontaVista preview kit to see if that will get me going in the right direction. I think the software will eventually be fine, but then organizing the FPGA correctly may be a challenge... anyone do this kind of thing already?

thanks again

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The PowerPCs in the Virtex FPGAs do not have hardware support for keeping their caches coherent with each other. Read the memory management section of the user guide for more information on this.

Lack of hardware support for cache coherency is a problem if you want to use an SMP OS. You can however run two separate copies of an OS, each with their own memory space. You can also have shared memory regions, but you will have to deal with cache coherency issues in software.

Would that solve your problem?


John McCaskill

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Thanks for the response Josh,

I knew about the ability to run two separate OSes, but really do want to get an SMP machine out of the Virtex II. I will check out the mem management section like you advised. I would like to avoid software solutions to this issue. Honestly, I am a bit surprised that more information isn't readily available on using the hard cores in an SMP fashion. If anyone else has any advice or references to pass along, I would appreciate it.


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