free 8 Channel Frequency meter for all FPGA owners :)

Impressive. Can you add to your web pages, a brief overview of the design, covering

- Appx MAX Ctr limit, either from SW estimate, or from a bench test (typ), and the LOGIC resources used

- Counter performance, typically digits/second for reciprocal Ctrs, or simply gate times and count rates, for the really vanilla ones ?

- Output choices - your examples seem to be PC-centric. Any options for LCD module output ( as on some eval PCBs ?)

jg

channel

At the moment I only have working proof of concept implementation using plain vanilla non optimized 32 bit gated counters. The max speed estimate could not be accurate as I dont know the target device speed grade - from thumb data the current implementation would support

I might be able to push the max input frequency to the max toggle rate of the fastest on chip flip-flop on some FPGAs and I may also be able to support clock speed beyound that by doing tap-delay line sampling. Also supported will be use of MGT as clock input yielding to max frequency to about little less than 1/2 of the MGT max bitrate.

Loading device for application Par from file '3s1500.nph' in environment Device utilization summary: Number of Slices 270 out of 13312 2% Number of BSCANs 1 out of 1 100% Number of BUFGMUXs 8 out of 8 100%

gate time is free from less than 1ms to 10years+ if you want to wait :) hm after doing slight mod to the ipcore what I see when measuring

this was impressive repeat stability when using PC based software controlled gate timing!

for ratiometric measurement where one clock input is reference for others the relative max error is worst case +2 clock per measurement

The presented approuch is PC centric, or optionally some FPGA board with ucCLinux could use another FPGA as well (in that case the absolute measurement would be even more exact and referenced to the main FPGA clock)

The PC based approuch support ANY FPGA (from supported vendor/family) without ZERO knowledge about external connections and requires no reference clock to be present at the FPGA pins.

It would not be possible to support the same flexibility on existing eval boards - another approuch would be required, and for you - work in that directions is also partially been done. So FPGA standalone version will also be offered but I would need to setup a 'board support database' and a bunch of scripts to compile the designs for all known boards.

Antti