Hi
I assume this not so widely known and most likely has not so much actual use, but in some cases it may be useful to use JTAG pins as general purpose IO, that is to some extent possible with most modern FPGAs. I havent checked actel and lattice for this issue yet, but for Xilinx and Altera its possible
some explanation and simple source code for Altera and Xilinx is available
it is to be noted that even Altera SCAN primitive has 1 versus 2 (in pre V4 Xilinx) USER commands available Altera SCAN primitive is more flexible than the Xilinx one. This is due to the fact that in Altera all 4 JTAG pins can be monitored from FPGA fabric. In case of multi chip chains this allows the SCAN primitive to be used as JTAG debugger or tracer for scan chain troubleshooting (when working with other devices in the chain). Xilinx V4 as of advertized should have this feature too, but I have not verified if it is actually there or in what form it is useable.
Antti