Bus expansion

Mar 26, 2005 1 Replies

Hello,



how do I extend buses in Quartus Schematic Editor? Say, for instance, there is an input "phase_offset[23..0]" and a component which expects a 32-bit wide vector. I would like to map phase_offset to the upper 24 bits of the vector and hardwire the remaining bits to 0. In VHDL it would be:



[...] port map (vec => phase_offset & "00000000") [...]

For non-constant data I have already figured it out:


  1. Create a bus using the Orthogonal Bus Tool;
  2. Select the bus and then in its properties fill the "name" field with e.g. shifter_out[29..14], phase_out[15..3].

However, it does not work with constants.



My attempt: phase_offset[23..0],0,0,0,0,0,0,0,0 Quartus: Error: Node "0" is missing source



My attempt: phase_offset[23..0],"00000000" Quartus: Error: Illegal wire or bus name phase_offset[23..0],"0000000" of type signal



My attempt: use the megafunction wizard to insert a constant by the name of "Z" and value 0, then write phase_offset[23..0],Z,Z,Z,Z,Z,Z,Z,Z Quartus: Error: Node "Z" is missing source.



So then, how should I express my intentions? :-)



Best regards Piotr Wyderski



Hi Piotr,

Maybe this is not the best way.. but it works!!

Draw a bus line and give it a name, for example "a[7..0]". then connect this bus to a GND. Now on the input of the component which expects the 32bit vector you can have a bus line named "phase_offset[23..0],a[7..0]"

Hope it works for you too, let me know if I wasn't clear enough.

Christos dot Zamantzas at CERN dot ch

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