Field-Programmable Gate Arrays

FPGA sensitivities

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I meas...

4 comments posted 5yrs

posted by jlarkin

4 comments posted 5yrs posted by jlarkin

Active HDL Entity Retention

I have multiple entities in a file. I renamed one of them. The design bro wser now shows both the old entity and the ne...

4 comments posted 5yrs

posted by gnuarm.deletethisbit

4 comments posted 5yrs posted by gnuarm.deletethisbit

Multi-FPGA Interconnection: latest techniques

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited...

9 comments posted 5yrs

posted by gparthu

9 comments posted 5yrs posted by gparthu

Is there any way to get a different font for code sections?

When I make posts to this forum and have code to show, I do something like this: [code] module xyz (); // ... endmodule...

1 comments posted 5yrs

posted by kvnsmnsn

1 comments posted 5yrs posted by kvnsmnsn

How powerful is Verilog at using parameters to specify designs?

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter intege...

21 comments posted 5yrs

posted by kvnsmnsn

21 comments posted 5yrs posted by kvnsmnsn

Exponential Regression by XSG

I want to perform an exponential regression function by using the Xilinx system generator. To support fixed-point data,...

0 comments posted 5yrs

posted by mjzoob

0 comments posted 5yrs posted by mjzoob

exponential regression in XSG

Hi Guys, I hope everybody is fine. I would like to perform an exponential regression function by using the Xilinx system...

1 comments posted 5yrs

posted by mjzoob

1 comments posted 5yrs posted by mjzoob

Is it illegal to use an (enum) as a Verilog function input?

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean val...

1 comments posted 5yrs

posted by kvnsmnsn

1 comments posted 5yrs posted by kvnsmnsn

Can anyone explain "cannot currently create a parameter of type" compilation error message?

I've written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit,...

5 comments posted 5yrs

posted by kvnsmnsn

5 comments posted 5yrs posted by kvnsmnsn

Can a Verilog function take a boolean argument?

I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument,...

1 comments posted 5yrs

posted by kvnsmnsn

1 comments posted 5yrs posted by kvnsmnsn

Non-binary NCO Modulus

I recall digging deeply into NCO design some years ago. I am trying to rem ember the dirty details of what I had learne...

8 comments posted 5yrs

posted by gnuarm.deletethisbit

8 comments posted 5yrs posted by gnuarm.deletethisbit

Gowin FPGA Oddities

Gowin seems to have some nice configuration modes in their parts. Of cours e they have an auto boot from internal flash...

27 comments posted 5yrs

posted by gnuarm.deletethisbit

27 comments posted 5yrs posted by gnuarm.deletethisbit

Trenz FPGA Module

I'm interested in the Trenz FPGA Module with the Gowin GW1NR-LV9QN88 on boa rd. The price is a bit high... well, I gues...

5 comments posted 5yrs

posted by gnuarm.deletethisbit

5 comments posted 5yrs posted by gnuarm.deletethisbit

DE10 Standard Audio Demos not working

Hello, I bought the DE10 Standard and am having issues trying to run the demos rel ated to audio. I am trying to run th...

5 comments posted 5yrs

posted by dayalnandan28

5 comments posted 5yrs posted by dayalnandan28

Active HDL and the Case of the Haunted Cursor

Active HDL is really starting to piss me off. I can't understand some of t he things it does. Now the cursor won't stay...

1 comments posted 5yrs

posted by gnuarm.deletethisbit

1 comments posted 5yrs posted by gnuarm.deletethisbit