What is wrong with low level code?

hat I was coding at a very low level, which was true; I was referring to XO R gates, NAND gates, NOR gates, and NOT gates. Is there something wrong wit h writing my code at such a low level? If I have a fairly good understandin g of how my algorithm needs to run at such a low level, then what is wrong with writing that kind of low level code?

Nothing wrong with it as such, but it is less efficient and requires a lot of extra typing. When you say you "code at a very low level" I assume you are instantiating gates and wiring them together rather than just inferring gates using logic operators in assignments? If so, you can infer many, ma ny gates with a simple assignment of an expression to a signal like, A

It's not wrong, but:

1. It may make your code harder for read, for someone who isn't familiar with its workings. That someone could be yourself if you come back to the code in a decade's time.

1. The task you're trying to do probably doesn't fall naturally into a representation of NAND and NOR gates. So why not enter the problem in its natural state, rather than transform it first in your head? That way there's fewer opportunities for mistakes.

2. It may lull you into a false sense of security, because (unless you're instantiating vendor-specific primitives) the first thing any synthesis tool will do is throw away your gate representation. At which point the assumptions you may bring to your gate representation (eg about gate delays) no longer hold.

Theo

hat I was coding at a very low level, which was true; I was referring to XO R gates, NAND gates, NOR gates, and NOT gates. Is there something wrong wit h writing my code at such a low level? If I have a fairly good understandin g of how my algorithm needs to run at such a low level, then what is wrong with writing that kind of low level code?

Unless the algorithm specification that you're trying to implement is writt en in terms of such gates, then long term support of that code would be a r eason why coding at a low level is 'wrong'.

Kevin Jennings

As others have said readability is everything.

One time when I wrote at a low level was when trying to maximise speed when pipe-lining numerical algorithms.

There are times when it's appropriate.

If not in this thread I may have mentioned a former poster here who used sc hematics for hierarchical construction allowing specification of relative a nd absolute positioning within a layout. He only converted to VHDL when he was able to do the same specification of location attributes. Then he nev er looked back. He was essentially designing at the LUT level and simplify ing the design process by using hierarchical constructs eliminating much of the detail design process.

This was largely practical for his work because he was designing similar ci rcuits repeatedly, but mostly because he was being paid to do designs no on e else could pull off really. The combination of speed and density was har d to achieve. Today the tools are better and the parts are MUCH bigger mak ing large, fast designs easier to do without massive libraries of hand hewn designs much less common.

So wiring together such things as gates is very uncommon these days. It is well worth the while to learn how to describe your design in HDL rather th an instantiating gates and such.

On Tuesday, October 6, 2020 at 5:22:11 PM UTC-7, snipped-for-privacy@gmail.com wr ote:

s well worth the while to learn how to describe your design in HDL rather t han instantiating gates and such.

Okay, I'm willing to learn how to describe my design in HDL, preferably Ver ilog, since that's what I've concentrated on. How would I go about learning how to write higher level Verilog, rather "than instantiating gates and su ch"? I'll include my source code as it stands right now in my next post. I guess I'd just like to know how to code it at a higher level.

// (c) Kevin Simonson 2020

module lessThan #( parameter nmBits = 1) ( output lssThn , input [ nmBits-1:0] leftOp , input [ nmBits-1:0] rightOp);

typedef enum { CORNER, E_LEAF, N_LEAF, SIDE, E_INTERIOR, N_INTERIOR } nodeType;

localparam integer nmNodes = (nmBits

is well worth the while to learn how to describe your design in HDL rather than instantiating gates and such.

erilog, since that's what I've concentrated on. How would I go about learni ng how to write higher level Verilog, rather "than instantiating gates and such"? I'll include my source code as it stands right now in my next post. I guess I'd just like to know how to code it at a higher level.

Sorry, it is too painful for me to read that sort of code. I don't say tha t as an insult, simply that Verilog is a second language to me so I'm not c lear what all the operators are, etc.

If you want to add two numbers, you write

I found the top level module declaration (third line, duh!) and it looks like you are implementing a subtraction, I'm guessing the carry out is the flag.

In RTL this would be something like...

Out

snipped-for-privacy@gmail.com (Rick C.): "In RTL this would be something like... / Out

Ack! Rick, sorry for calling you Rich. It was a typo.

. / Out

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