Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Active HDL and the Case of the Haunted Cursor

Active HDL is really starting to piss me off. I can't understand some of t he things it does. Now the cursor won't stay...
1 comments posted 6yrs
posted by gnuarm.deletethisbit
1 comments posted 6yrs posted by gnuarm.deletethisbit

Go To VHDL Resource

I started a new design the other day and realized I had forgotten which web sites were good VHDL resources. There are r...
2 comments posted 6yrs
posted by gnuarm.deletethisbit
2 comments posted 6yrs posted by gnuarm.deletethisbit

Bit Swizzling

I'm not sure where to ask this question, so I pushed it out to several groups. You need not reply to all of them if you...
7 comments posted 6yrs
posted by rick.c.hodgin
7 comments posted 6yrs posted by rick.c.hodgin

ADCs in FPGAs

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all dig...
23 comments posted 6yrs
posted by gnuarm.deletethisbit
23 comments posted 6yrs posted by gnuarm.deletethisbit

Are Gowin Serious Contenders?

I'm looking at using Gowin in a design and I not sure about them. They are being sold at Mouser, but the prices are not...
7 comments posted 6yrs
posted by gnuarm.deletethisbit
7 comments posted 6yrs posted by gnuarm.deletethisbit

iCE40 Ultra Family Data Sheet

Looking at section 4.5 the power up supply sequence is clearly stated to st art with Vcc/Vccpll, then to bring up SPI_V...
7 comments posted 6yrs
posted by gnuarm.deletethisbit
7 comments posted 6yrs posted by gnuarm.deletethisbit

Potential New Design

I might be working on a smallish design shortly and I'm picking an FPGA. I don't have much in the way of requirments ye...
11 comments posted 6yrs
posted by gnuarm.deletethisbit
11 comments posted 6yrs posted by gnuarm.deletethisbit

Elastic buffer implementation

For this article : Implementing Latency-Insensitive Dataflow Blocks at http ://arcade.cs.columbia.edu/lid-memocode15.pd...
0 comments posted 6yrs
posted by feiphung
0 comments posted 6yrs posted by feiphung

Some preliminary help for an FPGA selection

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex reall...
3 comments posted 6yrs
posted by dp
3 comments posted 6yrs posted by dp

Entity-bound SDC file in Quartus Lite Edition?

Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be availabl...
1 comments posted 6yrs
posted by wzab01
1 comments posted 6yrs posted by wzab01