Is it illegal to use an (enum) as a Verilog function input?

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was wa iting for input on that I decided to rewrite a version of my Verilog code t o use an (enum) instead of a (boolean). Much to my amazement, it appears th at I can't use an (enum) as an input to a function either! I wrote the foll owing code:

  module useBin ();


typedef enum { ADD, MULTIPLY } binOp;

function integer execOp;      input integer left;      input integer right;      input   binOp op;    begin      execOp = op == ADD ? left + right : left * right;    end  endfunction

endmodule  

When I ran Icarus to simulate it I got:

  D:\Hf\Verilog\Unpacked\Common>ive useBin  \Icarus\bin\iverilog -g2009 -o useBin.out useBin.sv  useBin.sv:8: syntax error  useBin.sv:5: error: Syntax error defining function.


D:\Hf\Verilog\Unpacked\Common>  

I can kind of understand why a (boolean) might cause a problem when used as a function input, but why in the world would it be illegal to use an (enum ) like my (binOp) as a function input?