Is it illegal to use an (enum) as a Verilog function input?

I'm still very much interested in finding out whether or not it's possible
for a Verilog function to have a boolean value as input, but while I was wa
iting for input on that I decided to rewrite a version of my Verilog code t
o use an (enum) instead of a (boolean). Much to my amazement, it appears th
at I can't use an (enum) as an input to a function either! I wrote the foll
owing code:

module useBin ();
typedef enum { ADD, MULTIPLY } binOp;
function integer execOp;
input integer left;
input integer right;
input binOp op;
execOp = op == ADD ? left + right : left * right;

When I ran Icarus to simulate it I got:

D:\Hf\Verilog\Unpacked\Common>ive useBin
\Icarus\bin\iverilog -g2009 -o useBin.out syntax error error: Syntax error defining function.

I can kind of understand why a (boolean) might cause a problem when used as
a function input, but why in the world would it be illegal to use an (enum
) like my (binOp) as a function input?
Reply to
Kevin Simonson
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Enum, and any typedefs are all fine as SystemVerilog inputs to functions. They are all first class citizens. I can't spot the problem in your code by eye, but it should work fine.
As to "booleans" in Verilog there's no predefined "boolean" type in verilog. One just uses one bit signal. i.e. reg true_false; or bit true_false; // If you don't want to deal with x/z
Regards, Mark
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