Field-Programmable Gate Arrays

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xapp134 on sdram controllers: @ bits reordering?

In this design, and in others I've seen around, the bank bits are MSB. What would you think about reordering address bi...
1 comments posted 21yrs
posted by robertp
1 comments posted 21yrs posted by robertp

Shared bus on FPGA

I have a microprocessor core (Plasma from Opencores), I want to implement a shared bus (Data as well as Address) among...
3 comments posted 21yrs
posted by ankit.raizada
3 comments posted 21yrs posted by ankit.raizada

Problem with appnote XAPP622 (SDR LVDS)

Hi, in the introduction i find: "At SDR clock frequencies below the maximum operating frequency (420 MHz) of the Virtex...
1 comments posted 21yrs
posted by benjamin
1 comments posted 21yrs posted by benjamin

LVDS for lcd panel and RocketIO

Hi, I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS frequency is max 80 MHz. My fpga runs at 100 MHz...
4 comments posted 21yrs
posted by benjamin
4 comments posted 21yrs posted by benjamin

vhdl code for the 2-line lcd on xilinx boards

Hi, does anybody know where to find code for the 2-line lcd? For now I want to talk to the lcd without any processor (no...
1 comments posted 21yrs
posted by benjamin
1 comments posted 21yrs posted by benjamin

implement the JTAG MASTER --ACT8990 by using FPGA

I want to implement the JTAG MASTER --ACT8990 by using FPGA,Does wh have do the same thing? Could someone give me a hand...
8 comments posted 21yrs
posted by strayblue2003
8 comments posted 21yrs posted by strayblue2003

edk annual renewal cost?

I am fairly new to the FPGA world. I've been using Actel parts (Axcelerator family) at work but I would like to migrate...
1 comments posted 21yrs
posted by starfire151
1 comments posted 21yrs posted by starfire151

vhdl and clock-pin

Hi, when I use a CLK input-pin in vhdl in my top-level file, is this automatically the clk signal of my device? Or do I...
2 comments posted 21yrs
posted by benjamin
2 comments posted 21yrs posted by benjamin

Question about Xilinx OPB/PCI bridge

Hi, I am new using Xilinx EDK. The version I'm using is 6.3. I'd like to access OPB bus from PCI side. I'm Xilinx OPB/P...
0 comments posted 21yrs
posted by RizwanRasheed205
0 comments posted 21yrs posted by RizwanRasheed205

clk_div illigal connection

Hi, this is my code dcm1_1 : dcm1 port map ( CLKIN_IN => CLK, RST_IN => RESET, CLKFX_OUT => clk_20M, CLKIN_IBUFG_OUT =>...
1 comments posted 21yrs
posted by benjamin
1 comments posted 21yrs posted by benjamin

A PCI FPGA card I found on ebay

While browsing ebay I came across this - http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&category=11223&item=5766178884...
4 comments posted 21yrs
posted by randomdude
4 comments posted 21yrs posted by randomdude

ISE 7.1 won't play with EDK 6.3 ????

So I got ISE 7.1 on an old 32 bit box up and running. But now when I am trying to use EDK, I get: cpu08:~/projects/xsys...
1 comments posted 21yrs
posted by russelmann
1 comments posted 21yrs posted by russelmann

Neural Networks in FPGA

Has anyone investigated implementimg neural nets in FPGAs?
12 comments posted 21yrs
posted by e
12 comments posted 21yrs posted by e

EDK: Microblaze with XMdstub

hi, How do I setup my MicroBlaze design to use XMDStub for debugging my embedded design?I am using virtex-II pro ML310...
4 comments posted 21yrs
posted by kittyawake
4 comments posted 21yrs posted by kittyawake