Shared bus on FPGA

I have a microprocessor core (Plasma from Opencores), I want to implement a shared bus (Data as well as Address) among the this core and a number of other cores as well. If anyone has some experience about implememnting a shared bus please let me know. I have 2 ideas (1) to connect the cores in a daisy chain kind of fashion (2) to connect the cores using tri state logic. which will give me more performance benefit? Also other experiences, ideas and knowledge about nuances of this design are welcome.

Reply to
Ankit Raizada
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The entity for Plasma Core is as given below entity mlite_cpu is generic(memory_type : string := "DUAL_PORT";

--DUAL_PORT_XILINX_XC4000XLA adder_type : string := "DEFAULT"; --AREA_OPTIMIZED mult_type : string := "DEFAULT"; --AREA_OPTIMIZED shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED alu_type : string := "DEFAULT"; --AREA_OPTIMIZED pipeline_stages : natural := 3; accurate_timing : boolean := true); port(clk : in std_logic; reset_in : in std_logic; intr_in : in std_logic;

mem_address : out std_logic_vector(31 downto 0); mem_data_w : out std_logic_vector(31 downto 0); mem_data_r : in std_logic_vector(31 downto 0); mem_byte_sel: out std_logic_vector(3 downto 0); mem_write : out std_logic; mem_pause : in std_logic); end; --entity mlite_cpu

Reply to
Ankit Raizada

That's going to depend entirely on your traffic patterns.

Have you considered the OpenCores Wishbone?

Regards,

--
|              Mark McDougall                | "Electrical Engineers do it
|     |   with less resistance!"
Reply to
Mark McDougall

Only thing I can add is if you are using internal tri-state buffers in Xilinx FPGA, use negative true control signals. A tri-stated signal is read as a logic High.

Ankit Raizada wrote:

Reply to
Brijesh

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