xapp134 on sdram controllers: @ bits reordering?

In this design, and in others I've seen around, the bank bits are MSB.

What would you think about reordering address bits, so that MSB are plugged to row bits: the idea is to avoid the ACTIVE command latency, because MSB [so row bits] are less likely to change.

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Depending on your access pattern, this might help.

IIRC the SHARC DSP has the option to do this...

Cheers, Martin

TRW Conekt, Solihull, UK
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Martin Thompson

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